Memory with level shifting word line driver and method thereof

A memory comprising:

• a plurality of global word lines;
• global word line driver circuitry having a plurality of outputs, each output coupled to a corresponding global word line of the plurality of global word lines;
• address decode circuitry having an output to provide a predecode value;
• a local bit cell array comprising a plurality of local word lines;
• local word line driver circuitry having an input coupled to the output of the address decode circuitry, an input coupled to corresponding global word line of the plurality of global word lines, and a plurality of outputs, each output coupled to a corresponding local word line of the plurality of local word lines, wherein the local word line driver circuitry comprises a plurality of voltage level shifters, each voltage level shifter associated with a corresponding local word line of the local bit cell array;
• wherein the global word line driver circuitry and address decode circuitry are operable in a first voltage domain;
• and
• wherein the local bit cell array and local word line driver circuitry are operable in a second voltage domain different than the first voltage domain.