Semiconductor memory device and data erase method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsYasuhiko MATSUNAGA, Fumitaka ARAI
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Abstract
A semiconductor memory device includes a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first and second select transistors, a source line, and a bit line, wherein the first dummy cell is disposed on the source line side such that one end and the other end of the current path thereof are connected between the first select transistor and the memory cell, and a threshold voltage of the first dummy cell is higher than a neutral threshold voltage.
Claims18
A semiconductor memory device comprising:
- a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first select transistors each having a current path with one end connected to one end of a current path of an associated one of the memory cell strings, and a plurality of second select transistors each having a current path with one end connected to the other end of the current path of an associated one of the memory cell strings;
- a source line which is electrically connected to the other end of the current path of an associated one of the first select transistors;
- and
- a bit line which is electrically connected to the other end of the current path of an associated one of the second select transistors,
- wherein the first dummy cell is disposed on the source line side such that one end and the other end of the current path thereof are connected between the first select transistor and the memory cell, and a threshold voltage of the first dummy cell is higher than a neutral threshold voltage.
A semiconductor memory device comprising:
- a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells, a first dummy cell and a second dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first select transistors each having a current path with one end connected to one end of a current path of an associated one of the memory cell strings, and a plurality of second select transistors each having a current path with one end connected to the other end of the current path of an associated one of the memory cell strings;
- a source line which is electrically connected to the other end of the current path of an associated one of the first select transistors;
- and
- a bit line which is electrically connected to the other end of the current path of an associated one of the second select transistors,
- wherein the first dummy cell is disposed on the source line side such that one end and the other end of the current path thereof are connected between the first select transistor and the memory cell, and a threshold voltage of the first dummy cell is higher than a neutral threshold voltage, and
- the second dummy cell is disposed on the bit line side such that one end and the other end of the current path thereof are connected between the second select transistor and the memory cell.
A data erase method of a semiconductor memory device including a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first select transistors each having a current path with one end connected to one end of a current path of an associated one of the memory cell strings, and a plurality of second select transistors each having a current path with one end connected to the other end of the current path of an associated one of the memory cell strings, the method comprising:
- applying an erase voltage to a semiconductor substrate, applying a reference voltage to a word line which is connected to a control electrode of the memory cell, and applying a voltage, which has a value between the reference voltage and the erase voltage, to a first dummy word line which is connected to a control electrode of the first dummy cell.
Dependencies are inferred from the claim text.