Memory array using mechanical switch and method for operating thereof

A method for operating a memory array using a mechanical switch, in which the memory array comprises:

• a plurality of word lines;
• a plurality of bit lines intersecting each other with the plurality of word lines;
• a gate electrode connected to each of the word lines;
• a drain electrode spaced apart from the gate electrode and connected to a capacitor;
• and a source electrode, and the source electrode comprises:
• an anchor part spaced apart from the gate electrode and connected to each of the bit lines;
• a mobile part where a dimple is formed, the method comprising steps of:
• applying respectively the write voltages Vwrite or the erase voltages Verase having the different voltage magnitudes to the bit lines more than two selected from the plurality of bit lines;
• applying a voltage greater than a sum of a maximal write voltage Vwrite-max and a pull-in voltage Vpi of the write voltages Vwrite-max or the erase voltages Verase to the word lines selected from the plurality of word lines;
• and
• applying a voltage smaller than a sum of the erase voltage Verase and the pull-in voltage Vpi and a voltage smaller than a difference between the maximal write voltage Vwrite-max and the pull-in voltage Vpi to the bit lines unselected from the plurality of bit lines.

A method for operating a memory array using a mechanical switch, in which the memory array comprises:

• a plurality of word lines;
• a plurality of bit lines intersecting each other with the plurality of word lines;
• a gate electrode connected to each of the word lines;
• a drain electrode spaced apart from the gate electrode and connected to a capacitor;
• and a source electrode, and the source electrode comprises;
• an anchor part spaced apart from the gate electrode and connected to each of the bit lines and;
• a mobile part where a dimple is formed, the method comprising steps of:
• applying a write voltage Vwrite or an erase voltage Verase to the bit line selected from the plurality of bit lines;
• applying a voltage greater than a sum of the write voltages Vwrite and a pull-in voltage Vpi to the word lines selected from the plurality of word lines;
• and
• applying a voltage smaller than a sum of the erase voltage Verase and the pull-in voltage Vpi and a voltage greater than the write voltage Vwrite, or a voltage smaller than a difference between a voltage greater than the write voltage Vwrite and the pull-in voltage Vpi and a voltage greater than the erase voltage Verase to the word lines unselected from the plurality of word lines.

A memory array using a mechanical switch, the memory array comprising:

• a plurality of word lines;
• a plurality of bit lines intersecting each other with the plurality of word lines;
• and
• a plurality of the mechanical switches,
• the mechanical switch disposed at an intersection of the plurality of word lines and the plurality of bit lines, and comprising:
• a gate electrode connected to each of the word lines;
• a drain electrode spaced apart from the gate electrode and connected to a capacitor;
• and
• a source electrode,
• the source electrode comprising:
• an anchor part spaced apart from the gate electrode and connected to each of the bit lines;
• a mobile part extended from the anchor part and spaced apart from the gate electrode;
• and
• a dimple extended from the mobile part and formed in a protrusion shape.