Analog to digital converter with a series of delay units

An analog-to-digital converter, comprising:

• L (L is an integer equal to or higher than two) core units, each core unit comprising:
• a pulse delay circuit, having M (M is an integer equal to or higher than two) delay units, that transmits a pulse signal through the delay units serially arranged and delays the pulse signal in each delay unit by a delay time corresponding to a level of an analog signal;
• a data holding unit that latches the pulse signal delayed in each delay unit at N (N is an integer-equal to or higher than two) sampling times to hold each of M×N values at M×N sampling points of the pulse signal as a piece of latched data;
• and
• a converted data producing unit that receives the M×N pieces of latched data from the data holding unit as a single piece of combined data composed of the latched data arranged in an order corresponding to an arranging order of the M×N sampling points in the pulse signal, converts the combined data into numeral data, corresponding to a position of the pulse signal in the pulse delay circuit, at one time as converted digital data corresponding to the level of the analog signal;
• and
• an adder circuit that calculates a sum of the pieces of converted digital data obtained in the core units as final converted digital data corresponding to the level of the analog signal.

An analog-to-digital converter, comprising:

• a pulse delay circuit, having M (M is an integer equal to or higher than two) delay units, that transmits a pulse signal through the delay units serially arranged and delays the pulse signal in each delay unit by a delay time corresponding to a level of an analog signal;
• N (N is an integer equal to or higher than two) coding circuits, wherein each coding circuit latches M outputs of the delay units at one of N sampling times every sampling period to hold M values at M sampling points of the M outputs as M pieces of latched data, calculates numeral data corresponding to a position of the pulse signal in the pulse delay circuit from a single piece of combined data, which is composed of the M latched data arranged in an order corresponding to an arranging order of the M sampling points in the pulse signal, at one time as converted digital data corresponding to the level of the analog signal every sampling period;
• and
• an adding circuit that calculates a sum of the pieces of converted digital data produced in the coding circuits as final converted digital data, corresponding to the level of the analog signal, every sampling period, the adding circuit comprising:
• a plurality of adder units arranged in a binary tree structure of P (N=2P) stages such that 2P-k (k is an integer ranging from 1 to P) adder units among the adder units are arranged in parallel to one another on the k-stage, wherein each of the adder units arranged on the k-stage has
• an adder that calculates a sum of two pieces of converted digital data received from two adder units of the (k−1)-stage, and
• a latch circuit that latches the sum calculated in the adder and outputs the latched sum to one adder of the (k−1)-th stage as converted digital data;
• and
• an adder clock generating circuit that generates P adder clocks specifying P latching times at predetermined delay time intervals every sampling period, such that each delay time interval is shorter than the sampling period, and supplies the adder clocks to the latch circuits such that the latch circuits of each stage perform latching operations in synchronization with one of the adder clocks and such that the latching time in the k-th stage is later than the latching time in the (k−1)-th stage by one delay time interval.