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US 2009/0021404 A1Published application
Variable resistance logic
AssigneeMicron Technology, Inc.
InventorYASUO SATOH
Life of this patent
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Abstract
A system comprising a control logic that generates a code having n digits, a translation logic coupled to the control logic that translates the code to a new code having greater than n digits, and a variable resistance logic coupled to the translation logic and comprising greater than n semiconductor devices. A resistance associated with the variable resistance logic depends on activation statuses of the semiconductor devices. The translation logic adjusts at least some of the semiconductor devices in accordance with the new code.
Claims31
A system, comprising:
- control logic that generates a code having n digits;
- translation logic coupled to the control logic and that translates the code to a new code having greater than n digits;
- and
- variable resistance logic coupled to the translation logic and comprising greater than n semiconductor devices, a resistance associated with the variable resistance logic depending on activation statuses of the semiconductor devices;
- wherein the translation logic adjusts at least some of said semiconductor devices in accordance with said new code.
2 more elements
A system, comprising:
- control logic adapted to generate a first code having n digits;
- translation logic that maps each of 2n binary codes to a different one of 2>n binary codes;
- and
- variable resistance logic comprising >n transistors arranged in parallel;
- wherein the translation logic receives said first binary code, translates said first binary code to a corresponding binary code having >n digits, and provides the corresponding binary code to the variable resistance logic;
- wherein the variable resistance logic adjusts said >n transistors in accordance with said corresponding binary code.
3 more elements
A system, comprising:
- a first resistor comprising a first variable resistor;
- and
- a second resistor comprising a semiconductor-based variable resistor, the second resistor coupled to a non-variable resistor having a target resistance;
- and
- control logic adapted to calibrate said semiconductor-based variable resistor in accordance with said target resistance using a translation logic which maps each of 2n binary codes to one of 2>n binary codes, said 2n binary codes generated by the control logic and said 2>n binary codes associated with >n transistors arranged in parallel in said semiconductor-based variable resistor;
- wherein the first variable resistor is calibrated in accordance with said semiconductor-based variable resistor.
3 more elements
A system, comprising:
- a first resistor comprising a first NMOS-based variable resistor having n transistors arranged in parallel and a first PMOS-based variable resistor having n transistors arranged in parallel;
- a second resistor comprising a second PMOS-based resistor having n transistors arranged in parallel and a second NMOS-based resistor having n transistors arranged in parallel;
- a target resistor coupled to the second PMOS-based resistor and having a target calibration resistance;
- a counter adapted to generate a plurality of codes having n−1 digits;
- and
- translation logic that maps each one of said codes having n−1 digits to a different code having n digits and applies at least one of said different codes to the n transistors of the second PMOS-based resistor;
- wherein the translation logic applies a plurality of said different codes to the n transistors of the second PMOS-based resistor until a voltage across the target resistor is a particular fraction of a supply voltage provided to the second resistor;
- wherein a resistance of the second NMOS-based resistor is calibrated to a resistance of the second PMOS-based resistor;
- wherein settings associated with the n transistors of the second PMOS-based resistor are applied to the n transistors of the first PMOS-based resistor and settings associated with the n transistors of the second NMOS-based resistor are applied to the n transistors of the first NMOS-based resistor.
6 more elements
A method, comprising:
- generating a plurality of first codes having n−1digits;
- translating said plurality of first codes having n−1 digits to second codes having n digits;
- applying said second codes having n digits to variable resistance logic comprising n transistors, the n transistors being arranged in parallel;
- and
- if a voltage across a target resistor corresponds to a particular fraction of a supply voltage provided to the variable resistance logic coupled to the target resistor, applying a current second code associated with the n transistors of the variable resistance logic to transistors associated with a different variable resistance logic.
2 more elements
A resistor, comprising:
- a first resistor:
- a variable resistor coupled in parallel with the first resistor;
- and
- circuit logic coupled to the variable resistor and adapted to control the variable resistor;
- wherein the variable resistor and the circuit logic are adapted to collectively and selectively provide a plurality of resistances for the resistor;
- wherein the variable resistor is adapted to permit 2n discrete resistance values;
- and
- wherein the control logic is adapted to control the variable resistor to provide less than the 2n discrete resistance values.
5 more elements
Dependencies are inferred from the claim text.