Voltage controlled oscillator capable of operating in a wide frequency range

A voltage controlled oscillator, comprising:

• a first NMOS transistor having a base terminal configured to receive an input signal INP and a drain terminal connected to an output node OUTN;
• a second NMOS transistor having a base terminal configured to receive an input signal INN and a drain terminal connected to an output node OUTP;
• a third NMOS transistor having a source terminal connected to a low voltage supply VSS and a drain terminal connected to source terminals of the first NMOS transistor and the second NMOS transistor, wherein the third NMOS transistor has a base terminal configured to receive an enable signal EN;
• a first PMOS transistor having a base terminal connected to the output node OUTP, a drain terminal connected to the output node OUTN, and a source terminal connected to a high voltage supply VDD;
• a second PMOS transistor having a base terminal connected to the output node OUTN, a drain terminal connected to the output node OUTP, and a source terminal connected to the VDD, wherein the output node OUTN and the output node OUTP are configured to output at least one oscillation signal;
• a fourth NMOS transistor coupled between the output node OUTN and VSS;
• a fifth NMOS transistor coupled between the output node OUTP and VSS, wherein base terminals of the fourth NMOS transistor and the fifth NMOS transistor are configured to receive a voltage control signal VCTRL;
• a first capacitor connected between the fourth NMOS transistor and VSS;
• and
• a second capacitor connected between the fifth NMOS transistor and VSS.

A voltage controlled oscillator, comprising:

• a converter comprising a first input INN, a second input INP, and an output FOUT, wherein the converter is configured to output an oscillation signal at the output FOUT;
• N serially connected delay cells, wherein N is an integer larger than 1, comprising:
• an Nth delay cell comprising a first output OUTN connected to the first input INN of the converter and a second output OUTP connected to the second input INP of the converter;
• an (N−1)th delay cell comprising a first output OUTN connected to the first input INN of the Nth delay cell and a second output OUTP connected to the second input INP of the Nth delay cell;
• and
• a first delay cell comprising a first output OUTN connected to the first input INN of the second delay cell and a second output OUTP connected to the second input INP of the second delay cell, the first delay cell further comprising a first input INN connected to the second output OUTP of the Nth delay cell and a second input INP connected to the first output OUTN of the Nth delay cell,
• wherein at least one of the N serially connected delay cells comprises:
• a first NMOS transistor having a base terminal configured to receive an input signal INP and a drain terminal connected to a first output OUTN associated with the one of the N serially connected delay cells;
• a second NMOS transistor having a base terminal configured to receive an input signal INN and a drain terminal connected to a second output OUTP associated with the one of the N serially connected delay cells;
• a third NMOS transistor having a source terminal connected to a low voltage supply VSS and a drain terminal connected to source terminals of the first NMOS transistor and the second NMOS transistor;
• a first PMOS transistor having a base terminal connected to the first output OUTP associated with the one of the N serially connected delay cells and a drain terminal connected to the second output OUTN associated with the one of the N serially connected delay cells;
• and
• a second PMOS transistor having a base terminal connected to the second output OUTN associated with the one of the N serially connected delay cells, and a drain terminal connected to the first output OUTP associated with the one of the N serially connected delay cells, wherein the output node OUTN and the output node OUTP associated with the one of the N serially connected delay cells are configured to output at least one oscillation signal.