US 2009/0021312 A1 · PLL circuit

Abstract

It has been difficult that conventional PLL circuits have a suppression characteristic of suppressing the phase noise which is free of variation due to temperature and individual difference and stable in a wide frequency band. The present invention provides a PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.

Claims5

Dependent claims

A PLL circuit comprising a voltage controlled oscillator oscillating a frequency corresponding to a control voltage, a reference frequency oscillator oscillating a constant frequency, a phase comparator comparing the output frequency of the reference frequency oscillator with the output frequency of the voltage controlled oscillator and outputting a phase difference, and a loop filter generating the control voltage on the basis of the phase difference,

wherein loop gain varying means for varying a loop gain of the PLL circuit is disposed at an output stage of the phase comparator,
wherein the loop gain varying means includes a first register storing a first parameter for adjusting a loop gain and a first multiplier multiplying the first parameter output from the first register by the output of the phase comparator, and
wherein the PLL circuit further includes a controller setting the first parameter in the first register on the basis of a device state and a use condition.

wherein loop gain varying means for varying a loop gain of the PLL circuit and response characteristic varying means for varying a response characteristic of the PLL circuit are disposed at an output stage of the phase comparator,
wherein the loop gain varying means includes a first register storing a first parameter for adjusting a loop gain and a first multiplier multiplying the first parameter output from the first register by the output of the phase comparator,
wherein the response characteristic varying means includes a second register storing a second parameter for adjusting a response characteristic and a second multiplier receiving the branched output of the first multiplier and multiplying the second parameter output from the second register by the output of the first multiplier, and
wherein the PLL circuit further includes a controller setting the first parameter and the second parameter in the first register and the second register, respectively, on the basis of a device state and a use condition.

1 more element

Dependencies are inferred from the claim text.

PLL circuit

Life of this patent

PLL circuit

Life of this patent

Abstract

Claims5