System and method for phase-locked loop (pll) for high-speed memory interface (hsmi)

The circuit of 8, further comprising a self-biased circuit so as to constrain an amount of current to be consumed by a VCO independent of the VCO's oscillating frequency.

A hi-speed memory interface device comprising a phase locked loop (PLL) having a plurality of voltage control oscillators (VCOs) arranged to control one or more oscillation frequencies, a plurality of pre-dividers interoperably arranged in a predetermined manner with one another and a phase detector to provide balanced frequencies to the phase detector, a divider circuit, a loop filter, a charge-pump circuit for charging common mode voltages, and a proportional to absolute temperature (PTAT) block.

A hi-speed memory device have an interface and an external long loop delay, comprising:

• a phase locked loop (PLL) having a plurality of voltage control oscillators (VCOs) arranged to control one or more oscillation frequencies, a divider circuit, a loop filter, a charge-pump circuit for charging common mode voltages, a self-biasing current, and a plurality of pre-positioned pre-dividers being of a quantity M, wherein each pre-divider has a divider ratio of 1/M and is positioned before one of an input reference clock or a loop back clock, wherein a loop delay effect is reduced in relation to the divider ratio.

An apparatus comprising:

• a common mode architecture having a means for comparing phases of a reference signal and a feedback signal, a plurality of voltage control oscillators (VCO) means arranged to control one or more oscillation frequencies, a plurality of pre-dividing means interoperably arranged in a predetermined manner with one another, a phase detecting means to provide balanced frequencies to the phase detector, a divider means for dividing a reference clock, a loop filter means, a charge-pump circuit means for charging common mode voltages, a self-biasing means, wherein a quantity of M pre-dividers are positioned, each having a divider ratio of 1/M, before one of an input reference clock or a loop back clock, where M is greater than one.

An improved PLL having integrated circuit capable of generating duty cycle clocks, comprising:

• a voltage control oscillator (VCO) arranged to control one or more oscillation frequencies, a plurality of pre-dividers interoperably arranged in a predetermined manner with one another and a phase detector to provide balanced frequencies to the phase detector, a divider circuit, a loop filter, and a charge-pump circuit for charging common mode voltages, wherein the improved PLL is devoid of a voltage to current (V-I) circuit.