Signal Delay Element, Method and Integrated Circuit Device for Frequency Adjustment of Electronic Signals
AssigneeInternational Business Machines Corporation
InventorsFlorian Braun, Cedric Lichtenau, Thomas Pflueger, Ulrich Weiss
Life of this patent
Estimating the term…
Abstract
The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.
Claims21
A method for frequency adjustment of electronic signals in an integrated electronic circuit comprising the steps of
- providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element;
- providing an edge of said input signal of said signal delay element;
- and
- delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.
A signal delay element in an electronic circuit, comprising
- a programmable delay line with a signal input for receiving an input signal and a signal output for outputting an output signal;
- a phase compare and reset logic connected to the signal input and receiving an output signal from said programmable delay line as well as from a delay look ahead block, where said delay look ahead block is also connected to the signal output of said programmable delay line;
- an adder block, wherein a delay step size definition block is connected to an input of the adder block;
- a counter block, wherein said counter block is receiving input from said adder block and from said phase compare and reset logic;
- and
- a decoder block, wherein said adder block is connected to an input (80) of said counter block, said counter block is connected to an input (82) of said decoder block and said decoder block is connected to the programmable delay line.
An integrated circuit device comprising a signal delay element coupled to an output of a frequency generator for transforming a first frequency of an output signal of said frequency generator to a second frequency below said first frequency by aligning pulse edges of an output signal of said signal delay element to pulse edges of said output signal of said frequency generator.
Dependencies are inferred from the claim text.