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US 2009/0021231 A1Published application
Voltage regulator
AssigneeSeiko Instruments Inc.
InventorTakashi Imura
Life of this patent
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Abstract
Provided is a voltage regulator having satisfactory transient response characteristics. Because a PMOS (25) and an NMOS (24) pass drain currents (charge and discharge currents with respect to gate of PMOS (26)) based on the square of voltage (ΔIR) according to change (ΔI) in drain currents of NMOSs (16 and 17), a maximum value (Imax) of the charge and discharge currents becomes larger, transition time (t) of gate voltage of the PMOS (26) becomes shorter, and the transient response characteristics of the voltage regulator become better.
Claims3
A voltage regulator, comprising:
- an input terminal to which input voltage is input;
- an output terminal for outputting output voltage;
- an output transistor provided between the input terminal and the output terminal;
- a voltage divider circuit provided at the output terminal for dividing the output voltage and for outputting divided voltage;
- a reference voltage circuit for outputting reference voltage;
- and
- a differential amplifier circuit including a first input transistor having a gate to which the reference voltage is input and a second input transistor having a gate to which the divided voltage is input, for controlling the output transistor based on a square of voltage according to change in drain currents of the input transistors.
4 more elements
Dependencies are inferred from the claim text.