STRUCTURES OF AND METHODS FOR FORMING VERTICALLY ALIGNED Si WIRE ARRAYS
AssigneeCalifornia Institute of Technology
InventorsBrendan M. KAYES, Michael A. Filler, Nathan S. Lewis, Harry A. Atwater
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Abstract
A structure consisting of vertically aligned wire arrays on a Si substrate and a method for producing such wire arrays. The wire arrays are fabricated and positioned on a substrate with an orientation and density particularly adapted for conversion of received light to energy. A patterned oxide layer is used to provide for wire arrays that exhibit narrow diameter and length distribution and provide for controlled wire position.
Claims20
A structure comprising:
- an ordered array of crystalline Si wires, wherein Si wires in a plurality of the crystalline Si wires have diameter dimensions generally orthogonal to length dimensions and wherein radii of the plurality of Si wires in the diameter dimensions are roughly equal to the minority carrier diffusion length of material comprising the Si wires.
A method for fabricating vertically aligned Si wire arrays comprising:
- forming a templating layer on a Si substrate;
- patterning the templating layer with a plurality of holes extending to the Si substrate;
- depositing a catalyst into one or more of the holes in the templating layer;
- and
- growing wires on the substrate at a temperature between 950° C. to 1100° C. and applying a growth gas comprising SiCl4.
A method for fabricating semiconductor structures comprising:
- forming a templating layer on a Si substrate;
- patterning the templating layer with an array of holes extending to the Si substrate;
- forming catalyst islands within one or more holes in the array of holes;
- and
- growing semiconductor structures on the Si substrate at a temperature between about 950° C. to about 1050° C. and applying a growth gas comprising SiCl4.
Dependencies are inferred from the claim text.