US 2009/0020828 A1Published application

Semiconductor device and its manufacturing method

OwnerTakayuki YAMADAinventor

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Abstract

A first MIS transistor includes a first source/drain region formed outside a first sidewall spacer in a first active region, a first silicide film formed on the first source/drain region, and a stressor insulating film formed on a first gate electrode, the first sidewall spacer, and the first silicide film. A second MIS transistor includes a second source/drain region formed outside a second sidewall spacer in a second active region, a first protection film formed, extending over a second gate electrode, the second sidewall spacer, and a portion of the second source/drain region, and including a first protection insulating film and a second protection insulating film, a second silicide film formed outside the first protection film on the second source/drain region, and the stressor insulating film formed on the first protection film and the second silicide film.

Claims30

Dependent claims

A semiconductor device comprising a first MIS transistor and a second MIS transistor, wherein

the first MIS transistor includes:
a first gate insulating film formed on a first active region of a semiconductor substrate;
a first gate electrode formed on the first gate insulating film;
a first sidewall spacer formed on a side surface of the first gate electrode;
a first source/drain region formed outside the first sidewall spacer in the first active region;
a first silicide film formed on the first source/drain region;
and
a stressor insulating film formed on the first gate electrode, the first sidewall spacer, and the first silicide film, wherein the stressor insulating film generates a stress in a gate length direction in the first active region, and
the second MIS transistor includes:
a second gate insulating film formed on a second active region of the semiconductor substrate;
a second gate electrode formed on the second gate insulating film;
a second sidewall spacer formed on a side surface of the second gate electrode;
a second source/drain region formed outside the second sidewall spacer in the second active region;
a first protection film formed, extending over the second gate electrode, the second sidewall spacer, and a portion of the second source/drain region, wherein the first protection film includes a first protection insulating film and a second protection insulating film formed on the first protection insulating film;
a second silicide film formed outside the first protection film on the second source/drain region;
and
the stressor insulating film formed on the first protection film and the second silicide film.

14 more elements

A method for manufacturing a semiconductor device, wherein the semiconductor device comprises a first MIS transistor formed in a first active region of a semiconductor substrate and a second MIS transistor formed in a second active region of the semiconductor substrate, the method comprising:

(a) forming, in the semiconductor substrate, an isolation region for separating the first active region and the second active region;
(b) forming a first gate electrode via a first gate insulating film on the first active region, and forming a second gate electrode via a second gate insulating film on the second active region;
(c) forming a first sidewall spacer on a side surface of the first gate electrode, and forming a second sidewall spacer on a side surface of the second gate electrode;
(d) forming a first source/drain region outside the first sidewall spacer in the first active region, and forming a second source/drain region outside the second sidewall spacer in the second active region;
(e) after step (d), forming a first protection film including a first protection insulating film and a second protection insulating film formed on the first protection insulating film, on the second gate electrode, the second sidewall spacer, and a portion of the second source/drain region;
(f) after step (e), forming a first silicide film outside the first sidewall spacer on the first source/drain region, and forming a second silicide film outside the first protection film on the second source/drain region;
and
(g) after step (f), forming a stressor insulating film on the semiconductor substrate.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/172,372Filed 14 Jul 2008
Priority: JP 2007-18851019 Jul 2007
Published: 22 Jan 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 30/792
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: comprising applied insulating layers, e.g. stress liners
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels
H10D 84/0184
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate sidewall spacers