Thin gate electrode cmos devices and methods of fabricating same
AssigneeInternational Business Machines Corporation
InventorsJack A. Mandelman, William Robert Tonti
Life of this patent
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Abstract
A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench.
Claims24
A structure, comprising:
- a source and a drain formed in a device region of a semiconductor substrate, said source and said drain separated by a channel region in said device region;
- a gate dielectric layer formed on a top surface of said substrate in said channel region and a metal or metal alloy gate electrode formed on a top surface of said gate dielectric layer, said gate electrode having sidewalls and a top surface;
- and
- a polysilicon line abutting and in electrical contact with at least one sidewall of said gate electrode, said polysilicon line having a first thickness in a direction perpendicular to a top surface of said substrate greater than a second thickness in said direction perpendicular to said top surface of said substrate of said gate electrode.
A structure, comprising:
- a source and a drain formed in a device region of a semiconductor substrate, said source and said drain separated by a channel region in said device region;
- a gate dielectric formed on a top surface of said substrate in said channel region and a metal or metal alloy gate electrode formed on a top surface of said gate dielectric layer;
- and
- wherein said gate electrode has a thickness of less than about 25 nm.
A method, comprising:
- (a) forming a dielectric trench isolation in a semiconductor substrate;
- (b) forming a first layer on a top surface of said semiconductor substrate;
- (c) patterning said first layer into a line, said line extending over said channel region and said trench isolation;
- (d) forming dielectric spacers on opposite sidewalls of said line, said spacers having inner walls abutting said line and outer walls away from said line;
- (e) forming a source and a drain separated by a channel region in said substrate where said substrate is not protected by said line or said spacers;
- (f) forming a second layer over said source, said drain and said trench isolation and said spacers;
- (h) removing said line from over said channel region to form a trench defined by said inner walls of said spacers and said top surface of said substrate;
- (i) forming a gate dielectric layer on said top surface of said substrate in said channel region;
- and
- (j) forming a metal or metal alloy gate electrode on a top surface of said gate dielectric layer, said gate electrode extending over said trench isolation, said gate electrode and said gate dielectric layer not filling said trench.
Dependencies are inferred from the claim text.