Channel-stressed semiconductor devices and methods of fabrication
AssigneeSamsung Electronics Co., Ltd.
InventorsHion-suck BAIK, Jong-bong PARK, Jung-yun WON, Hwa-sung RHEE, Byung-seo KIM, Ho LEE, Myung-sun KIM, Ji-hye YI
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Abstract
In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.
Claims33
A method of fabricating a semiconductor device, comprising:
- forming at least one capping layer over epitaxial source/drain regions of a PMOS device;
- forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and
- treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.
A method of manufacturing a semiconductor device, comprising:
- providing a substrate including an NMOS region and a PMOS region, and gate structures respectively located over the NMOS region and PMOS region;
- forming first and second trenches in the substrate adjacent the gate structure of the PMOS region;
- forming epitaxial source and drain regions within the first and second trenches, respectively;
- forming at least one capping layer over the epitaxial source and drain regions;
- forming a stress memorization (SM) layer over the NMOS and PMOS regions, including the at least one capping layer;
- and
- annealing the SM layer formed over the NMOS and PMOS regions.
A method of manufacturing a semiconductor device comprising interposing at least one capping layer between a PMOS device and a stress memorization (SM) layer, and treating the SM layer to induce tensile stress in an NMOS device located adjacent the PMOS device.
A semiconductor device, comprising:
- a PMOS device comprising a gate structure located over a substrate, epitaxial source and drain regions located in the substrate adjacent the gate structure, and a channel region located between the epitaxial source and drain regions;
- and
- an NMOS device comprising a gate structure located over the substrate, first and second recesses in a surface of the substrate adjacent the gate structure, source and drain regions formed in the substrate below the first and second recesses of the substrate, and a channel region located between the source and drain regions.
Dependencies are inferred from the claim text.