Aging device
AssigneeKabushiki Kaisha Toshiba
InventorsHiroshi Watanabe, Atsuhiro Kinoshita, Shigeki Kobayashi, Daisuke Hagishima
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Abstract
An aging device according to an embodiment of the present invention includes a semiconductor substrate, first and second diffusion layers provided in a first element region, a floating gate provided above a channel region between the first and second diffusion layers, and a control gate electrode provided beside the floating gate with an interval in the lateral direction. A coupling capacitance between the floating gate and the control gate electrode is larger than a coupling capacitance between the floating gate and the semiconductor substrate.
Claims20
An aging device comprising:
- a semiconductor substrate;
- an element isolation insulating layer provided in a surface region of the semiconductor substrate;
- a first element region surrounded by the element isolation insulating layer;
- first and second diffusion layers arranged in the first element region;
- a channel region provided between the first and second diffusion layers;
- a floating gate provided above the channel region;
- and
- a control gate electrode provided beside the floating gate with an interval in the lateral direction,
- wherein a coupling capacitance between the floating gate and the control gate electrode is larger than a coupling capacitance between the floating gate and the semiconductor substrate.
An aging device comprising:
- a semiconductor substrate;
- an element isolation insulating layer provided in a surface region of the semiconductor substrate;
- an element region surrounded by the element isolation insulating layer;
- first and second diffusion layers arranged in the element region;
- a channel region provided between the first and second diffusion layers;
- a floating gate provided above the channel region;
- and
- a control gate electrode provided beside the floating gate with an interval in a direction perpendicular to a direction in which the first and second diffusion layers is arranged,
- wherein a coupling capacitance between the floating gate and the control gate electrode is larger than a coupling capacitance between the floating gate and the semiconductor substrate.
Dependencies are inferred from the claim text.