Two-bit flash memory cell structure and method of making the same
OwnerWei-Ming Liao, Ming-Cheng Chang +1inventors
InventorsWei-Ming Liao, Ming-Cheng Chang, Jer-Chyi Wang
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Abstract
A flash memory cell includes a control gate oxide layer on a substrate, a T-shaped control gate on the control gate oxide layer, a floating gate disposed on two recessed sidewalls of the T-shaped control gate, an insulating layer between the control gate and the floating gate, a dielectric layer between the floating gate and the substrate, a spacer on the sidewall of the floating gate, a P+ source/drain region next to the spacer, and an N+ pocket region encompassing the P+ source/drain region and covering the area directly under the floating gate.
Claims12
A method for fabricating a flash memory device, comprising:
- providing a substrate having thereon a dielectric layer and a first silicon layer;
- forming a cavity in the first silicon layer and the dielectric layer to expose a portion of the substrate;
- forming a control gate oxide layer on the exposed substrate within the cavity;
- forming an insulating layer on interior surface of the cavity and on the first silicon layer;
- forming a second silicon layer on the insulating layer, wherein the second silicon layer fills the cavity;
- forming a photoresist pattern on the second silicon layer;
- performing an etching process to etch the second silicon layer, the insulating layer and the first silicon layer not covered by the photoresist pattern, thereby forming a T-shaped control gate and a floating gate;
- performing a tilt-angle ion implantation process to form an N+ pocket doping region under the floating gate;
- forming a spacer on a sidewall of the floating gate;
- and
- performing a heavy ion implantation process to form a P+ source/drain region in the substrate next to the spacer.
A flash memory cell, comprising:
- a substrate;
- a control gate oxide layer on the substrate;
- a T-shaped control gate on the control gate oxide layer;
- a floating gate disposed on two recessed sidewalls of the T-shaped control gate;
- an insulating layer between the control gate and the floating gate;
- a dielectric layer between the floating gate and the substrate;
- a spacer on a sidewall of the floating gate;
- a P+ source/drain region in the substrate next to the spacer;
- and
- an N+ pocket region encompassing the P+ source/drain region and covering an area directly under the floating gate.
Dependencies are inferred from the claim text.