Plasma display apparatus and semiconductor device

A semiconductor device for driving a plasma display apparatus having a first sustaining electrode, a second sustaining electrode connected to reference potential and cooperating with said first sustaining electrode to perform sustaining discharge through a discharge space, and an address electrode, with an electrical capacitance set up between said second sustaining electrode and said discharge space being larger than an electrical capacitance set up between said first sustaining electrode and said discharge space, comprising a drive circuit for applying voltage to said first sustaining electrode, wherein said drive circuit includes:

• a first switch element for passing light emission current while clamping its output voltage to a high level;
• a second switch element for passing light emission current while clamping its output voltage to a low level;
• and
• a third switch element for charging and discharging the capacitor formed between said first sustaining electrode and said discharge space through a coil, and
• wherein each of said first, second and third switch elements is comprised of an IGBT including:
• a first semiconductor layer of first conduction type;
• a second semiconductor layer of second conduction type laminated on said first semiconductor layer;
• a third semiconductor layer of second conduction type laminated on said second semiconductor layer and containing impurities at a lower concentration than said second semiconductor layer;
• a fourth semiconductor layer of first conduction type laminated on at least part of said third semiconductor layer and containing impurities at a higher concentration than said third semiconductor layer;
• a fifth semiconductor port of second conduction type formed in said fourth semiconductor layer and containing impurities at a higher concentration than said fourth semiconductor layer;
• a first main electrode in contact with said first semiconductor layer;
• a second main electrode in contact with said fourth semiconductor layer and said fifth semiconductor port;
• and
• an insulated gate port making contact with said fifth semiconductor port and passing through said fourth semiconductor layer to reach said third semiconductor layer.