Display device transferring data signal with clock
AssigneeSamsung Electronics Co., Ltd.
InventorsJae-Jin PARK, Dong-Uk PARK, Jin-Ho SEO
Life of this patent
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Abstract
A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n−1]) within the embedded clock data signal.
Claims15
A display device comprising:
- a panel;
- a timing controller generating an embedded clock data signal combining image data and a clock signal;
- and
- a column driver driving the panel in response to the embedded clock data signal,
- wherein data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and
- the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n−1]) within the embedded clock data signal.
A display device comprising:
- a timing controller configured to generate an embedded clock data signal wherein data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme,
- wherein each one of the three voltage levels corresponds respectively to a high, low, and middle state, and
- the embedded clock data signal comprises a dummy bit communicated in a first time period and having the middle state, and a clock bit communicated in a time period next to the first time period and having either the high state or the low state;
- and
- a column driver receiving the embedded clock data signal and recovering the clock bit from the embedded clock data signal,
- wherein the clock bit has the high state if a previous data bit within the embedded clock data signal has the middle state and a next previous data bit has the high state, but the clock bit has the low state if the previous data bit has the middle state and a next previous data has the low state.
Dependencies are inferred from the claim text.