Liquid crystal display panel with color washout improvement by scanning line coupling and applications of same

A liquid crystal display (LCD) panel with color washout improvement, comprising:

• a. a common line;
• b. a plurality of scanning lines, {Gn}, n=1, 2, . . . , N, spatially arranged along a row direction;
• c. a plurality of data lines, {Dm}, m=1, 2, . . . , M, spatially arranged crossing the plurality of scanning lines {Gn} along a column direction perpendicular to the row direction;
• and
• d. a plurality of pixels spatially arranged in the form of a matrix, each pixel, {Pn,m}, located between two neighboring scanning lines Gn, and Gn+1 and two neighboring data lines Dm and Dm+1, and comprising at least a first sub-pixel and a second sub-pixel, each of the first sub-pixel and the second sub-pixel comprising a transistor having a gate, a source and a drain, a liquid crystal (LC) capacitor having a first terminal and a second terminal, and a storage capacitor having a first terminal and a second terminal,
• wherein the gate, the source and the drain of the transistor T1 of the first sub-pixel are electrically coupled to the scanning line Gn, the data line Dn, and the source of the transistor T2 of the second sub-pixel, respectively;
• wherein the first terminal and the second terminal of the LC capacitor Clc1 of the first sub-pixel are electrically coupled to the drain of the transistor T1 of the first sub-pixel and the common line, respectively;
• wherein the first terminal of the storage capacitor Cst1 of the first sub-pixel is electrically coupled to the drain of the first transistor T1 of the first sub-pixel;
• wherein the gate and the drain of the transistor T2 of the second sub-pixel are electrically coupled to the scanning line Gn and the first terminal of the LC capacitor Clc2 of the second sub-pixel, respectively;
• wherein the second terminal of the LC capacitor Clc2 of the second sub-pixel is electrically coupled to the common line;
• wherein the first terminal of the storage capacitor Cst2 of the second sub-pixel is electrically coupled to the drain of the transistor T2 of the second sub-pixel;
• and
• wherein one of the second terminal of the storage capacitor Cst1 of the first sub-pixel and the second terminal of the storage capacitor Cst2 of the second sub-pixel is electrically coupled to the scanning line Gn−1 or the scanning line Gn+1, and the other of the second terminal of the storage capacitor Cst1 of the first sub-pixel and the second terminal of the storage capacitor Cst2 of the second sub-pixel is electrically coupled to the common line.