Serial-to-parallel conversion circuit and method of designing the same
AssigneeMitsubishi Heavy Industries, Ltd.
InventorsShigeru Ishii, Masaharu Nomachi
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Abstract
The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data and a strobe when a first-stage memory device in a shift register latches data and when the memory device holds the data; providing a logical circuit for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period.
Claims11
A method of designing a serial-to-parallel conversion circuit including a clock generator configured to generate a clock by taking the exclusive OR of received data and a strobe, and a register group including a plurality of memory devices sequentially latching the data in synchronization with a rising edge and a falling edge of the clock, the method comprising:
- determining a rule on the basis of the fact that logical values of the data and the strobe are guaranteed not to change substantially simultaneously when the memory devices of the register group latch the data and when the memory devices hold the data;
- providing a logical circuit configured to generate an output conforming to the rule at a data input side of the register group;
- and
- delaying data latch timing of the memory devices later than timing at which data input to the memory devices changes.
A serial-to-parallel conversion circuit comprising:
- a clock generator configured to generate a clock by taking the exclusive OR of received data and strobe;
- a register group including a plurality of memory devices and configured to sequentially latch the data in synchronization with a rising edge and a falling edge of the clock;
- and
- a logical circuit, provided at a data input side of the register group, configured to generate an output conforming to a rule based on the fact that logical values of the data and the strobe are guaranteed not to change substantially simultaneously when the memory devices of the register group latch the data and when the memory devices hold the data,
- wherein data latch timing of the memory devices is delayed later than timing at which data output from the logical circuit changes.
A serial-to-parallel conversion circuit comprising:
- a clock generator configured to generate a clock by taking the exclusive OR of received data and a strobe;
- a first register group including a plurality of memory devices, at least the memory device to which a signal is initially input being configured to latch the data at the falling edge of the clock;
- a second register group including a plurality of memory devices, at least the memory device to which the signal is initially input being configured to latch the data at the rising edge of the clock;
- a first logical circuit provided at an input side of the first register group and configured to output 0 when the data is 0 and the strobe is 1, to output 1 when the data is 1 and the strobe is 0, and to output a previous value when the data and the strobe are both 0 or both 1;
- and
- a second logical circuit provided at an input side of the second register group and configured to output 0 when the data is 0 and the strobe is 0, to output 1 when the data is 1 and the strobe is 1, and to output the previous value when the data and the strobe have different values from each other.
Dependencies are inferred from the claim text.