Device and method for biasing a transistor amplifier

A device as claimed in any one of the preceding claims wherein the biasing circuit includes a resistor-divider for controllably varying the DC-voltage signal.

A device as claimed in any one of the preceding claims wherein the low-pass circuit includes a capacitor operatively coupled with at least one of a diode, a MOSFET, and a JFET of the biasing circuit, wherein the capacitor forms a first low-pass filter with an impedance of the at least one diode, MOSFET and JFET.

A device as claimed in any one of the preceding claims including a control current source wherein the control current source is adapted to automatically trigger adjustment of an impedance of at least one of a diode, MOSFET and JFET of the sub-circuit whereby said adjustment configures the sub-circuit to mirror the DC-voltage signal of the resistor-divider at the output node of the sub-circuit.

A device as claimed in any one of the preceding claims wherein a capacitive sensor is operatively coupled to the first input terminal of the transistor amplifier.

A device as claimed in any one of the preceding claims wherein the sub-circuit of the biasing circuit includes a PMOS and an NMOS MOSFET, wherein the drains of the PMOS and NMOS MOSFETs are operatively coupled to the first input terminal of the transistor amplifier, and gates of the PMOS AND NMOS MOSFETS are operatively coupled to different voltage potentials of the resistor-divider.

A device as claimed in any one of the preceding claims wherein the device is fabricated on an integrated circuit chip.

A low-pass filter adapted for use in filtering out a voltage ripple in a supply voltage signal, the voltage ripple being generated by a voltage multiplier device during voltage step-up conversion of the supply voltage signal before said supply voltage signal is fed to a capacitive sensor, the low-pass filter including a capacitor operatively coupled with a first and second diode, said first and second diodes being adapted for operative coupling in parallel between a terminal of the capacitor and an output terminal of the voltage multiplier device, said diodes being arranged in reverse polarity relative to each other in parallel.