Calibration circuit, semiconductor device including the same, and memory module
AssigneeElpida Memory, Inc.
InventorsShunji Kuwahara, Hiroki Fujisawa
Life of this patent
Estimating the term…
Abstract
A calibration circuit includes: a replica buffer that drives a calibration terminal; a pre-emphasis circuit connected in parallel to the replica buffer; and an up-down counter that changes impedances of the replica buffer and the pre-emphasis circuit. A replica control circuit causes the replica buffer to conduct based on an impedance code, and a pre-emphasis control circuit causes the pre-emphasis circuit to conduct in an initial stage of a conducting period of the replica buffer. Thereby, even when an external resistor is shared among a plurality of semiconductor devices, for example, a voltage appearing in the calibration terminal can be stabilized at a higher speed.
Claims18
A semiconductor device having a calibration circuit, the calibration circuit comprising:
- a first replica buffer that drives a calibration terminal;
- a first pre-emphasis circuit connected in parallel to the first replica buffer;
- a control unit that changes an impedance of the first replica buffer based on a voltage appearing at least at the calibration terminal, wherein
- the control unit brings the first pre-emphasis circuit into an active state during an initial stage of an active period of the first replica buffer.
A memory module comprising a semiconductor device having a calibration terminal, a circuit board on which the semiconductor device is mounted, and a resister mounted on the circuit board and connected to the calibration terminal, wherein the semiconductor device includes:
- a data output terminal and an output buffer that drives the data output terminal, wherein the calibration circuit includes:
- a first replica buffer that drives the calibration terminal;
- a first pre-emphasis circuit connected in parallel to the first replica buffer;
- a control unit that changes an impedance of the first replica buffer based on a voltage appearing at least at the calibration terminal,
- wherein the control unit brings the first pre-emphasis circuit into an active state during an initial stage of an active period of the first replica buffer, and at least a part of the output buffer has a circuit configuration identical to that of the replica buffer.
Dependencies are inferred from the claim text.