Semiconductor memory device and method of generating chip enable signal thereof

A method of generating a chip enable signal of a semiconductor memory device in which a plurality of memory chips and an interface chip are stacked, each memory chip comprising first through n-th input nodes and first through n-th output nodes, and the first through n-th input nodes of one of two adjacent memory chips are respectively connected to the first through n-th output nodes of the other of the two adjacent memory chips, the method comprising:

• setting 2-bit input signals applied to the first and second input nodes as less significant 2-bit control signals of n-bit control signals and performing a logic AND operation on by the less significant 2-bit control signals to generate AND operated signals;
• performing a logic XOR operation on each of the AND operated signals and each bit signal of more significant n−2-bit input signals applied to the third to n-th input nodes to generate n−2-bit control signals;
• outputting the signal applied to the second input node through a first output node, outputting an inverted signal of the signal applied to the first input node through a second output node, and outputting the more significant n−2-bit input signals through third to n-th output nodes, respectively;
• storing and outputting the control signal during an MRS operation;
• and
• generating the chip enable signal during a normal operation when the control signal is equal to a chip ID signal output from the interface chip.

A method of generating a chip enable signal of a semiconductor memory device in which a plurality of memory chips and an interface chip are stacked, each memory chip comprising first through n-th input nodes and first through n-th output nodes, and the first through n-th input nodes of one of two adjacent memory chips are respectively connected to the first through n-th output nodes of the other of the two adjacent memory chips, the method comprising:

• generating input signals applied to the first through n-th input nodes as n-bit control signals;
• performing a logic AND operation on the input signals applied to the first through n-th input nodes and less significant bit signals of the respective input signals applied to the first through n-th input nodes and outputting respective sum signals on each of the input signals through second through n-th input nodes and respective bit signals excluding n-th bit signal of respective AND operated signals obtained by performing the logic AND operation to second through n-th output nodes, respectively;
• storing and outputting the control signal during an MRS operation;
• and
• generating the chip enable signal during a normal operation when the control signal is equal to a chip ID signal output from the interface chip.