Power supply voltage detection circuit and semiconductor integrated circuit device
AssigneeNEC Electronics Corporation
InventorsManabu Kitabatake, Yuji Tada, Kouji Naganawa, Tsuyoshi Hirakawa, Ichiro Mizuguchi
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Abstract
A semiconductor integrated circuit device includes a first chip, a second chip to transmit and receive data to and from the first chip, and a through circuit provided in the first chip to transfer a clock signal and a test signal to the second chip. The clock signal and the test signal is inputted from an external device. The through circuit adjusts timing relation between the clock signal and the test signal based on a timing adjust signal. The timing adjust signal is inputted from the external device.
Claims18
A semiconductor integrated circuit device comprising:
- a first chip;
- a second chip to transmit and receive data to and from the first chip;
- and
- a through circuit provided in the first chip to transfer a clock signal and a test signal to the second chip, the clock signal and the test signal being inputted from an external device;
- wherein the through circuit adjusts timing relation between the clock signal and the test signal based on a timing adjust signal, the timing adjust signal being inputted from the external device.
A method of testing a semiconductor integrated circuit device having a first chip and a second chip in a single package, the second chip being accessible only through the first chip, comprising:
- inputting a clock signal and a test signal from an external device to the first chip, the clock signal and the test signal being to be inputted to the second chip;
- determining whether or not the test signal satisfies specified values for a set-up time and a hold time with respect to the clock signal in the first chip;
- if the test signal does not satisfy the specified value, searching for a pass range for the test signal to satisfy the specified values for the set-up time and the hold time with respect to the clock signal by using a timing adjust signal, the phase of the timing adjust signal being controlled by the external device;
- correcting the output timing of the test signal in accordance with the pass range in the first chip;
- and
- sending out the test signal to the second chip.
Dependencies are inferred from the claim text.