Interposer chip, method of manufacturing the interposer chip, and multi-chip package having the interposer chip
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-Seok Lim, Hyo-Dong Ban
Life of this patent
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Abstract
An interposer chip in accordance includes an insulating layer, conductive patterns and a dummy pattern. The conductive patterns are formed on the insulating layer. The dummy pattern is formed on the insulating layer to suppress a bending of the insulating layer. Further, the dummy pattern can have first isolating grooves formed along peripherals of the conductive patterns to isolate the dummy pattern from the conductive patterns. Thus, the interposer chip is not vulnerable to being bent. Further, an electrical short between the conductive patterns through the dummy pattern caused by particles is substantially avoided.
Claims20
An interposer chip comprising:
- an insulating layer;
- conductive patterns formed on the insulating layer;
- and
- a dummy pattern formed on the insulating layer and configured to suppress a bending of the insulating layer, the dummy pattern being electrically isolated from the conductive patterns by first isolating grooves that are formed along a periphery of each of the conductive patterns.
A method of manufacturing an interposer chip, the method comprising:
- forming a conductive layer on an insulating layer;
- and
- forming first isolating grooves at the conductive layer to form conductive patterns and a dummy pattern electrically isolated from the conductive patterns by the first isolating grooves.
A multi-chip package comprising:
- a printed circuit board (PCB);
- a first semiconductor chip stacked on the PCB and being electrically connected to the PCB;
- an interposer chip including an insulating layer that is stacked on the first semiconductor chip and has a size smaller than that of the first semiconductor chip, conductive patterns formed on the insulating layer and electrically connected to the first semiconductor chip, and a dummy pattern formed on the insulating layer that is configured to suppress a bending of the insulating layer, the dummy pattern being electrically isolated from the conductive patterns by first isolating grooves that are formed along a periphery of each of the conductive patterns;
- and
- a second semiconductor chip stacked on the interposer chip and electrically connected to the conductive patterns, the second semiconductor chip having a size smaller than that of the interposer chip.
Dependencies are inferred from the claim text.