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US 2009/0014894 A1Published application
Stacked semiconductor device and semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsKatsuhiro Ishida, Ryoji Matsushima
Life of this patent
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Abstract
A stacked semiconductor device includes a first semiconductor element mounted on a wiring board and a second semiconductor element stacked on the first semiconductor element. Electrode pads of the first and second semiconductor elements are electrically connected to connection pads of the wiring board via first and second metal wires. The second metal wire is wired so that a part thereof is in contact with an insulating protective film covering a surface of the first semiconductor element.
Claims20
A stacked semiconductor device, comprising:
- a circuit substrate having an element mounting portion and connection portions;
- a first semiconductor element, mounted on the element mounting portion of the circuit substrate, having a first element main body, first electrode pads disposed at a surface of the first element main body, and a first insulating protective film covering the surface while exposing the first electrode pads;
- a second semiconductor element, stacked on the first semiconductor element, having a second element main body, second electrode pads disposed at a surface of the second element main body, and a second insulating protective film covering the surface while exposing the second electrode pads;
- first metal wires electrically connecting the connection portions and the first electrode pads;
- second metal wires electrically connecting the connection portions and the second electrode pads, the second metal wires being wired so that a part thereof is in contact with the first insulating protective film;
- and
- a resin-sealing portion sealing the first and second semiconductor elements together with the first and second metal wires.
4 more elements
A semiconductor memory device, comprising:
- a circuit substrate having an element mounting portion and connection portions;
- a memory element group including at least one semiconductor memory element mounted on the element mounting portion of the circuit substrate, the semiconductor memory element having an element main body, first electrode pads disposed at a surface of the element main body, and an insulating protective film covering the surface while exposing the first electrode pads;
- a controller element, stacked on the memory element group, having second electrode pads;
- first metal wires electrically connecting the connection portions and the first electrode pads;
- second metal wires electrically connecting the connection portions and the second electrode pads, the second metal wires being wired so that a part thereof is in contact with the insulating protective film of the semiconductor memory element;
- and
- a resin-sealing portion sealing the memory element group and the controller element together with the first and second metal wires.
4 more elements
Dependencies are inferred from the claim text.