Multi-chip semiconductor device

A multi-chip semiconductor device comprising:

• a first wiring substrate having a first opening formed in a central portion and a plurality of first electrode terminals formed on a front surface thereof near the first opening,
• a second wiring substrate stacked on the first wiring substrate and having a second opening of an area larger than that of the first opening formed in a central portion and a plurality of second electrode terminals electrically connected to the plurality of first electrode terminals and formed on a front surface thereof near the second opening,
• a first semiconductor chip having a plurality of first bump electrodes formed on a front surface thereof,
• a second semiconductor chip which has a plurality of second bump electrodes containing a plurality of bump electrodes for connection with an exterior arranged and formed on a front surface thereof and is arranged with the front surface thereof set to face the front surface of the first semiconductor chip with the first and second wiring substrates disposed therebetween, those of the plurality of second bump electrodes other than the bump electrodes for connection with the exterior being electrically connected to the plurality of first bump electrodes of the first semiconductor chip in the first and second openings of the first and second wiring substrates and the plurality of second bump electrodes for connection with the exterior being electrically connected to the plurality of first electrode terminals of the first wiring substrate,
• a package substrate which has a plurality of electrodes for connection with the exterior formed on a front surface thereof, whose back surface is adhered to a back surface of the second semiconductor chip and which has a plurality of third electrode terminals electrically connected to the plurality of electrodes for connection with the exterior and is formed on the back surface thereof, and
• a plurality of third bump electrodes which electrically connect the plurality of third electrode terminals of the package substrate with the plurality of second electrode terminals of the second wiring substrate.

A multi-chip semiconductor device comprising:

• a wiring substrate having an opening in a central portion, a plurality of first electrode terminals arranged and formed on a front surface thereof near the opening, a plurality of second electrode terminals arranged and formed on the front surface of a peripheral portion thereof and a plurality of wirings which electrically connect corresponding ones of the plurality of first and second electrode terminals to one another and formed on the front surface,
• a first semiconductor chip having a plurality of first bump electrodes arranged and formed on a front surface thereof,
• a second semiconductor chip which has a plurality of second bump electrodes containing a plurality of bump electrodes for connection with an exterior arranged and formed on a front surface thereof and is arranged with the front surface thereof set to face the front surface of the first semiconductor chip with the wiring substrate disposed therebetween, those of the plurality of second bump electrodes other than the plurality of bump electrodes for connection with the exterior being electrically connected to the plurality of first bump electrodes of the first semiconductor chip in the opening of the wiring substrate and the plurality of second bump electrodes for connection with the exterior being electrically connected to the plurality of first electrode terminals of the wiring substrate, and
• a third semiconductor chip adhered to a back surface of the first semiconductor chip.