US 2009/0014879 A1 · Semiconductor device and method of manufacturing the same

Abstract

In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

Claims28

Dependent claims

A method of manufacturing a semiconductor device, comprising:

forming an insulation layer on a semiconductor including various conductive structures, and planarizing the insulation layer;
partially removing portions of the insulation layer to form at least one opening in the insulation layer, the substrate being partially exposed through the at least one opening;
forming a barrier layer on a sidewall and bottom of the at least one opening, the barrier layer including a residual metal layer formed on the bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer formed on the residual metal layer and an upper sidewall of the at least one opening;
and
forming a metal plug in the at least one opening by filling up the at least one opening with a metal material.

2 more elements

A semiconductor device comprising:

a semiconductor substrate including various conductive structures;
an insulation layer on the substrate to cover the conductive structures in such a configuration that spaces between the conductive structures are filled with the insulation layer and an upper surface of the insulation layer is planarized;
at least one opening formed through the insulation layer and partially exposing the substrate and a tungsten plug formed in the at least one opening;
a barrier layer interposed between the tungsten plug and the insulation layer, a lower portion of the barrier layer adjacent to the substrate including a tungsten layer and a tungsten nitride layer and an upper portion of the barrier layer adjacent to the insulation layer including a tungsten nitride layer;
and
an insulation interlayer on the tungsten plug and the insulation layer, the insulation interlayer including a via hole through which the tungsten plug is exposed;
a conductive line filling up the via hole and electrically connected to the tungsten plug.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor device and method of manufacturing the same

Life of this patent

Semiconductor device and method of manufacturing the same

Life of this patent

Abstract

Claims28