Semiconductor device package with bump overlying a polymer layer

A semiconductor device comprising:

• a substrate having an integrated circuit formed on a front surface of the substrate and a plurality of conductive bond pads formed at the front surface for making electrical interconnections to the integrated circuit;
• a wafer passivation layer on the front surface of the substrate, wherein the wafer passivation layer has openings to expose at least a portion of the conductive bond pads;
• a polymer layer overlying the wafer passivation layer, wherein the polymer layer has openings to expose a central portion of the conductive bond pads;
• an under-bump metallization layer overlying and in contact with the polymer layer, wherein the under-bump metallization layer contacts the conductive bond pads through the openings in the polymer layer;
• a plurality of solder bumps, each being secured to a portion of the under-bump metallization layer;
• and
• wherein each portion of the under-bump metallization layer securing one of the solder bumps has a bottom surface area and wherein less than about 30% of the bottom surface area is in metal-to-metal contact with its respective conductive bond pad.

A semiconductor device comprising:

• a substrate having an integrated circuit formed on a front surface of the substrate and a plurality of conductive bond pads formed at the front surface for making electrical interconnections to the integrated circuit;
• a wafer passivation layer on the front surface of the substrate, wherein the wafer passivation layer has openings to expose at least a portion of the conductive bond pads;
• a polymer layer overlying the wafer passivation layer, wherein the polymer layer overlaps and contacts a portion of the top surface of the conductive bond pads and has openings to expose a central portion of the conductive bond pads;
• a patterned under-bump metallization layer overlying and in contact with the polymer layer, wherein the under-bump metallization layer comprises titanium and contacts the conductive bond pads through the openings in the polymer layer;
• and
• a plurality of solder bumps, wherein at least a portion of each of the solder bumps is positioned above one of the conductive bond pads and secured to a portion of the under-bump metallization layer.

A method for forming a semiconductor device comprising a substrate having an integrated circuit formed on a front surface of the substrate and a plurality of conductive bond pads formed at the front surface for making electrical interconnections to the integrated circuit, the method comprising:

• forming a wafer passivation layer on the front surface of the substrate with openings to expose at least a portion of the conductive bond pads;
• forming a polymer layer overlying the wafer passivation layer, wherein the polymer layer overlaps and contacts a portion of the top surface of the conductive bond pads and the polymer layer has openings to expose a central portion of the conductive bond pads;
• forming a conductive layer positioned overlying and in contact with at least a portion of the polymer layer and to provide a plurality of solder bump pads, wherein the conductive layer contacts the conductive bond pads through the openings in the polymer layer;
• and
• mounting a plurality of solder bumps, each being secured to a corresponding one of the solder bump pads.