Interconnects for packaged semiconductor devices and methods for manufacturing such devices
AssigneeMicron Technology, Inc.
InventorsBoon Suan Jeung, Chia Yong Poo, Eng Meow Koon
Life of this patent
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Abstract
Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.
Claims34
A semiconductor assembly, comprising:
- a semiconductor die having a plurality of bond-sites;
- a dielectric support layer having a first side and a second side, wherein the die is attached to the second side of the support layer;
- a plurality of preformed conductive interconnects, wherein individual interconnects have a first portion in the support layer and a second portion spaced apart from the support layer;
- and
- a dielectric encapsulant between the interconnects and around at least a portion of the die.
A plurality of through package interconnects in a semiconductor assembly including a die, a dielectric support layer, and an encapsulant, the interconnects comprising:
- a plurality of preformed electrically conductive pins projecting from the support layer in a predetermined array outside of a footprint of the die, wherein the pins are arranged in the predetermined array apart from the encapsulant.
An intermediate article of manufacture of a semiconductor assembly, comprising:
- a dielectric support layer;
- a plurality of semiconductor dies attached to the support layer such that individual dies are at die sites across the support layer;
- and
- a plurality of preformed conductive pins having first portions retained in the support layer and second portions projecting from the support layer, wherein the pins are arranged in a plurality of discrete pin arrays, and wherein the second portions of the pins are free-standing without a solid material therebetween.
A system, comprising:
- at least one of a processor, a memory device and an input or output device, wherein at least one of the processor, memory device and input or output device includes a semiconductor assembly comprising
- a die having a plurality of bond-sites;
- a dielectric support layer, wherein the die is attached to the support layer;
- a plurality of preformed conductive interconnects projecting from the support layer, wherein individual interconnects have a first portion in the support layer;
- and
- a dielectric encapsulant molded between the interconnects and around at least a portion of the die.
A method of forming a semiconductor assembly comprising:
- retaining an array of preformed interconnects in a support member before disposing an encapsulant between the interconnects;
- positioning a die relative to the array of interconnects;
- and
- disposing an encapsulant between the interconnects and over at least a portion of the die after positioning the die relative to the interconnects.
A method of forming packaged assembly, comprising:
- inserting a plurality of preformed pins in a support layer, wherein individual pins have a first portion in the support layer and a second portion opposite the first portion, wherein the support layer at least partially retains the pins in a predetermined array;
- positioning a die on a first surface of the support layer;
- encasing at least a portion of the die and the pins in an encapsulant;
- and
- exposing the first and second portions of the pins.
Dependencies are inferred from the claim text.