US 2009/0014843 A1Published application

Manufacturing process and structure of through silicon via

AssigneeRenesas Electronics Corporation

InventorsMichihiro KAWASHITA, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa

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Abstract

A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.

Claims20

Dependent claims

A manufacturing method of a semiconductor device, comprising the steps of:

(a) forming an interlayer insulating film on a semiconductor element formed on a first surface of a semiconductor substrate, and forming a pad electrically connected to the semiconductor element via a wiring formed in the interlayer insulating film on a surface of the interlayer insulating film;
(b) forming a first resist film on a second surface of the semiconductor substrate on a side opposite to the first surface;
(c) patterning the first resist film to form a first opening at a position facing to the pad;
(d) forming a first hole, which exposes the interlayer insulating film on a bottom surface, in the semiconductor substrate by etching the semiconductor substrate with using the first resist film, in which the first opening is formed, as a mask;
(e) removing the first resist film;
(f) etching the interlayer insulating film exposed on the bottom surface of the first hole, thereby forming the bottom surface of the first hole at a position on the interlayer insulating film and closer to the pad than an interface between the semiconductor substrate and the interlayer insulating film;
(g) forming an insulating film on the second surface of the semiconductor substrate including an inner wall of the first hole;
(h) forming a second resist film on the insulating film;
(i) patterning the second resist film to form a second opening with a diameter smaller than that of the first hole in the bottom surface of the first hole;
(j) forming a second hole, which exposes the pad on a bottom surface, by etching the insulating film and the interlayer insulating film with using the second resist film, in which the second opening is formed, as a mask;
and
(k) forming a conductive film on the second surface of the semiconductor substrate including an inner wall of the first hole and an inner wall of the second hole and then patterning the conductive film, thereby forming a through silicon via reaching the first surface from the second surface of the semiconductor substrate and electrically connected to the pad,
wherein a surface of the interlayer insulating film on a side of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate, and
a surface of the conductive film has a step shape reflecting a step difference between the second surface of the semiconductor substrate and the bottom surface of the first hole.

11 more elements

A manufacturing method of a semiconductor device, comprising the steps of:

(a) forming an interlayer insulating film on a semiconductor element formed on a first surface of a semiconductor substrate, and forming a pad electrically connected to the semiconductor element via a wiring formed in the interlayer insulating film on a surface of the interlayer insulating film;
(b) forming a first resist film on a second surface of the semiconductor substrate on a side opposite to the first surface;
(c) patterning the first resist film to form a first opening at a position facing to the pad;
(d) forming a first hole, which exposes the interlayer insulating film on a bottom surface, in the semiconductor substrate by etching the semiconductor substrate with using the first resist film, in which the first opening is formed, as a mask;
(e) removing the first resist film;
(f) etching the interlayer insulating film exposed on the bottom surface of the first hole, thereby forming the bottom surface of the first hole at a position on the interlayer insulating film and closer to the pad than an interface between the semiconductor substrate and the interlayer insulating film;
(g) forming a photosensitive insulating film on the second surface of the semiconductor substrate including an inner wall of the first hole;
(h) patterning the photosensitive insulating film to form a second opening with a diameter smaller than that of the first hole in the bottom surface of the first hole;
(i) forming a second hole, which exposes the pad on a bottom surface, by etching the interlayer insulating film with using the photosensitive insulating film, in which the second opening is formed, as a mask;
and
(j) forming a conductive film on the second surface of the semiconductor substrate including an inner wall of the first hole and an inner wall of the second hole and then patterning the conductive film, thereby forming a through silicon via reaching the first surface from the second surface of the semiconductor substrate and electrically connected to the pad,
wherein a surface of the interlayer insulating film on a side of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate, and
a surface of the conductive film has a step shape reflecting a step difference between the second surface of the semiconductor substrate and the bottom surface of the first hole.

10 more elements

A semiconductor device, comprising:

(a) a semiconductor substrate;
(b) a semiconductor element formed on a first surface of the semiconductor substrate;
(c) an interlayer insulating film formed on the first surface of the semiconductor substrate;
(d) a pad formed on the interlayer insulating film;
(e) a bump electrode formed on the pad;
and
(f) a through silicon via reaching the pad from a second surface of the semiconductor substrate on a side opposite to the first surface,
wherein the through silicon via includes:
(f1) a first hole reaching the interlayer insulating film from the second surface of the semiconductor substrate on a side opposite to the first surface, the first hole having a bottom surface formed to a position closer to the pad than an interface between the interlayer insulating film and the semiconductor substrate;
(f2) a second hole having a diameter smaller than that of the first hole and reaching the pad from the bottom surface of the first hole;
(f3) an insulating film formed on a bottom surface and a side surface of the first hole and the second surface of the semiconductor substrate;
and
(f4) a conductive film formed on a bottom surface and a side surface of the second hole, a bottom surface and a side surface of the first hole via the insulating film, and the second surface of the semiconductor substrate, and electrically connected to the pad,
wherein a surface of the interlayer insulating film on a side of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate, and
a surface of the conductive film has a step shape reflecting a step difference between the second surface of the semiconductor substrate and the bottom surface of the first hole.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/133,828Filed 5 Jun 2008
Priority: JP 2007-1502896 Jun 2007
Published: 15 Jan 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification25 codes

H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 20/0234
The interconnections being through-semiconductor vias: comprising etching via holes that stop on pads or on electrodes
H10W 20/0242
The interconnections being through-semiconductor vias: comprising etching via holes from the back sides of the chips, wafers or substrates