Memory Array with a Selector Connected to Multiple Resistive Cells

An integrated circuit structure comprising:

• a transistor comprising a first, a second and a third terminal;
• a contact plug connected to the first terminal;
• a metal line overlying and connected to the contact plug;
• a first resistive memory cell having a first bottom electrode overlying and connected to the metal line;
• and
• a second resistive memory cell having a second bottom electrode overlying and connected to the metal line.

A memory array comprising a plurality of resistive memory cells arranged in a plurality of rows and columns, the memory array comprising:

• a plurality of word-lines extending in a first direction;
• a plurality of bit-lines extending in a second direction perpendicular to the first direction;
• a plurality of transistors connected to the plurality of word-lines, wherein each of the plurality of transistors comprises a first terminal, a second terminal, and a third terminal, and wherein the second terminal of each of the plurality of transistors is connected to a word-line in the plurality of word-lines;
• a first and a second contact plug connected to a first terminal of one of the plurality of transistors;
• a first resistive memory cell in the plurality of resistive memory cells, wherein the first resistive memory cell comprises a first end and a second end, and wherein the first end is connected to the first contact plug, and the second end is connected to a first bit-line in the plurality of bit-lines;
• and
• a second resistive memory cell in the plurality of resistive memory cells, wherein the second resistive memory cell comprises a third end and a fourth end, and wherein the third end is connected to the second contact plug, and the fourth end is connected to a second bit-line in the plurality of bit-lines.