Method for fabricating shallow trench isolation and method for fabricating transistor

A method comprising:

• defining an active area;
• forming a shallow trench isolation structure to isolate between NMOS and PMOS areas;
• forming a gate pattern over an active area of the NMOS and PMOS areas;
• performing an ion implant process over the active area of the PMOS area exposed through the gate pattern over the PMOS area to apply a compressive stress to a channel region of the PMOS area;
• forming N type and P type lightly doped drain regions by performing an impurity ion implantation process thereon;
• forming a gate spacer over a sidewall of the gate pattern;
• and
• forming N type and P type source/drain areas through an impurity ion implantation process.

An apparatus comprising:

• a semiconductor substrate over which NMOS areas and PMOS areas are formed;
• a shallow trench isolation structure defining an active area over the NMOS and PMOS areas, and including an oxide layer formed within a trench formed over the semiconductor substrate and a barrier liner layer formed on the oxide layer;
• a first gate electrode formed on the active area of the PMOS area;
• a first channel region formed under the first gate electrode;
• and
• source/drain areas having implanted material providing a compressive stress to the first channel region.