Methods For Forming Self-Aligned Dual Stress Liners For CMOS Semiconductor Devices

A method for forming a self-aligned, dual stress liner for complementary metal oxide semiconductor (CMOS) devices, the method comprising:

• providing a semiconductor substrate comprising first and second device regions formed on an active surface of the semiconductor substrate and separated by an isolation region, the first and second device regions including respective first type and second type transistor devices having polyconductor gate electrode and the isolation region comprising a polyconductor line formed thereon;
• forming a first stress liner layer of silicon nitride over the first and second device regions conformally covering the first and second type transistor devices;
• forming a first insulating layer of silicon oxide over the first stress liner layer;
• photo lithographically patterning the first insulating layer to expose a portion of the first stress liner layer over the second device region and an adjacent portion of the isolation region, wherein the patterned first insulating layer forms a step structure comprising a substantially vertical sidewall disposed over the isolation region;
• anisotropically etching the exposed portion of the first stress liner layer in the second device region using the patterned first insulating layer of silicon oxide as an etch mask to form a patterned first stress liner layer having a patterned sidewall aligned to the vertical sidewall of the patterned first insulating layer;
• forming a second stress liner layer of silicon nitride that conformally covers the second type transistors in the second device region and an upper surface and the patterned sidewalls of the patterned first insulating layer and first stress liner layer, wherein a portion of the second stress liner layer that abuts the patterned sidewall of the first stress liner layer defines a gapless interface between the first and second stress liner layers;
• forming a second insulating layer of silicon oxide over the first and second device regions covering the second stress liner layer;
• planarizing the semiconductor substrate surface down to a level to expose portions of the first and second stress liner layers atop the polyconductor gate electrodes in the first and second device regions and the polyconductor line in the isolation region;
• and
• forming a third insulating layer of silicon oxide over the planarized semiconductor substrate surface covering the exposed portions of the first and second stress liner layers atop the polyconductor gate electrode and the polyconductor line.

A dual stress liner (DSL) complementary metal oxide semiconductor (CMOS) device, comprising:

• a semiconductor substrate comprising first and second device regions formed on an active surface of the semiconductor substrate and separated by an isolation region, the first and second device regions including respective first type and second type transistor devices having polyconductor gate electrode and the isolation region comprising a polyconductor line formed thereon;
• a self aligned DSL structure comprising a first stress liner layer conformally covering the first type transistor devices in the first device region and a portion of the polyconductor line in the isolation region and a second stress liner layer conformally covering the second type transistor devices in the second device region and a portion of the polyconductor line in the isolation region,
• a first layer of insulating material disposed in gaps between adjacent polyconductor gate electrodes in the first device region and in gaps between polyconductor gate electrodes in the first device region and the polyconductor line in the isolation region;
• a second layer of insulating material disposed in gaps between adjacent polyconductor gate electrodes in the second device region and in gaps between polyconductor gate electrodes in the second device region and the polyconductor line in the isolation region;
• a third layer of insulating material formed over the substrate surface covering the first and second insulating materials in the gaps and covering the portions of the first and second stress liner layers atop the polyconductor gate electrodes in the first and second device regions and the polyconductor line in the isolation region between polyconductor gate electrodes and polyconductor line.