Misfet, semiconductor device having the misfet and method of manufacturing the same
AssigneeFujitsu Limited
InventorMasashi SHIMA
Life of this patent
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Abstract
To solve the problem, a MISFET covered with an insulating film which generates stress is provided. The MISFET including a gate insulating film; a gate electrode disposed on the gate insulating film, the gate electrode including a polysilicon portion and a silicide portion; and a source/drain disposed adjacent to the gate electrode, in which the ratio between the polysilicon portion and the silicide portion is determined depending on a strain for enhancing the driving capability of the MISFET, the strain being generated on the basis of the stress through the gate electrode in a channel region of the MISFET.
Claims14
A MISFET covered with an insulating film which generates stress, the MISFET comprising:
- a gate insulating film disposed on a semiconductor substrate;
- a gate electrode disposed on the gate insulating film, the gate electrode including a polysilicon portion and a silicide portion;
- a source disposed adjacent to one side of the gate electrode;
- and
- a drain disposed adjacent to the other side of the gate electrode,
- wherein a ratio of length in a height direction of the polysilicon portion to length in a height direction of the silicide portion is determined depending on a strain for enhancing the driving capability of the MISFET, the strain being generated on the basis of the stress generated by the insulating film through the gate electrode in a channel region of the MISFET under the gate electrode.
A semiconductor device comprising:
- an N-type MISFET covered with an insulating film which generates tensile stress, a gate electrode of the N-type MISFET including a polysilicon portion and a silicide portion, Young's modulus of a silicide in the silicide portion being higher than Young's modulus of a polysilicon in the polysilicon portion, a ratio of length in a height direction of the polysilicon portion to length in a height direction of the silicide portion being in a range of 0.5 to 0.8;
- and
- a P-type MISFET covered with an insulating film which generates tensile stress, a gate electrode of the P-type MISFET including a polysilicon portion and a silicide portion, Young's modulus of a silicide in the silicide portion being higher than Young's modulus of a polysilicon in the polysilicon portion, a ratio of length in a height direction of the polysilicon portion to length in a height direction of the silicide portion being in a range of 0.6 to 0.9.
A semiconductor device comprising:
- an N-type MISFET covered with an insulating film which generates compressive stress, a gate electrode of the N-type MISFET including a polysilicon portion and a silicide portion, Young's modulus of a silicide in the silicide portion being lower than Young's modulus of a polysilicon in the polysilicon portion, and a ratio of length in a height direction of the polysilicon portion to length in a height direction of the silicide portion being in a range of 0.6 to 0.9;
- and
- a P-type MISFET covered with an insulating film which generates tensile stress, a gate electrode of the P-type MISFET including a polysilicon portion and a silicide portion, Young's modulus of a silicide in the silicide portion being lower than Young's modulus of a polysilicon in the polysilicon portion, a ratio of length in a height direction of the polysilicon portion to length in a height direction of the silicide portion being in a range of 0.6 to 0.9.
A method for manufacturing a MISFET covered with an insulating film which generates stress, the method comprising:
- forming a gate insulating film on a semiconductor substrate;
- forming a polysilicon pattern on the gate insulating film;
- forming a sidewall composed of an insulating material on a side surface of the polysilicon pattern;
- forming a metal layer on the polysilicon pattern;
- and
- forming a gate electrode by allowing a metal constituting the metal layer to react with polysilicon constituting the polysilicon pattern to form a silicide, the gate electrode being composed of the polysilicon which remains unreacted and the silicide,
- wherein a ratio of length in a height direction of the polysilicon portion to length in a height direction of the silicide portion is determined depending on a strain for enhancing the driving capability of the MISFET, the strain being generated on the basis of the stress generated by the insulating film through the gate electrode in a channel region of the MISFET under the gate electrode.
A method for manufacturing a semiconductor device provided with an N-type MISFET having a first gate electrode and a P-type MISFET having a second gate electrode formed on a principal surface of a semiconductor, the N-type MISFET and the P-type MISFET being covered with an insulating film which generates stress, the method comprising:
- forming a gate insulating film on a semiconductor substrate;
- forming a first polysilicon pattern and a second polysilicon pattern on the gate insulating film;
- forming a sidewall composed of an insulating material on a side surface of each of the first polysilicon pattern and the second polysilicon pattern;
- forming a metal layer on the first polysilicon pattern and the second polysilicon pattern;
- and
- forming a first gate electrode and a second electrode by allowing a metal constituting the metal layer to react with polysilicon constituting the first polysilicon pattern and the second polysilicon pattern to form a silicide, the first gate electrode and the second gate electrode being composed of the polysilicon which remains unreacted and the silicide,
- wherein a ratio of length in a height direction of the polysilicon portion to length in a height direction of the silicide portion in the first gate electrode is different from a ratio of length in a height direction of the polysilicon portion to length in a height direction of the silicide portion in the second gate electrode.
Dependencies are inferred from the claim text.