Semiconductor Device with Improved Contact Structure and Method of Forming Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
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Abstract
A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer connecting to a gate region of a MOS transistor or to a first contact. A butted contact structure abutting a source/drain region and a gate electrode includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer with one end resting on the gate electrode and the other end in contact with the first contact.
Claims20
A contact structure of a MOS transistor comprising:
- a first contact formed within and substantially co-planar with a first dielectric layer on a semiconductor substrate, wherein said first contact is in contact with a source/drain region of said MOS transistor;
- a second contact formed within and substantially co-planar with a second dielectric layer formed over the first dielectric layer, wherein said second contact overlaps said first contact;
- and
- a third contact formed at least partially within and substantially co-planar with a top surface of the second dielectric layer, wherein said third contact is in contact with a gate region of said MOS transistor.
A butted contact structure for MOS transistors comprising:
- a first contact formed within and substantially co-planar with a first dielectric layer on a semiconductor substrate, wherein said first contact is in contact with a source/drain region of a first MOS transistor;
- and
- a second contact formed at least partially within and substantially co-planar with a top surface of a second dielectric layer formed over the first dielectric layer, wherein said second contact overlaps said first contact at one end, and in contact with a gate electrode of a second MOS transistor at the other end.
A semiconductor SRAM unit cell comprising:
- a first PMOS pull-up transistor including a drain coupled to a high voltage supply node, a source coupled to a second storage node, and a gate coupled to a first storage node;
- a first NMOS pull-down transistor including a drain coupled to a low voltage supply node, a source coupled to the second storage node, and a gate coupled to the first storage node;
- a second PMOS pull-up transistor including a drain coupled to the high voltage supply node, a source coupled to the first storage node, and a gate coupled to the second storage node;
- a second NMOS pull-down transistor including a drain coupled to the low voltage supply node, a source coupled to the first storage node, and a gate coupled to the second storage node;
- a first dielectric layer formed over the first PMOS and NMOS transistors, the second PMOS and NMOS transistors;
- a first local interconnect electrically coupling the source of the first PMOS, the source of the first NMOS, the first local interconnect formed within and substantially co-planer with the first dielectric layer;
- a second local interconnect electrically coupling the source of the second PMOS, the source of the second NMOS, the second local interconnect formed within and substantially co-planer with the first dielectric layer;
- a second dielectric layer formed over the first dielectric layer, the first local interconnect and the second local interconnect;
- a third local interconnect over the first local interconnect, electrically coupling the first local interconnect and the gates of the second PMOS and NMOS, the third local interconnect formed at least partially within and substantially co-planer with a top surface of the second dielectric layer;
- and
- a fourth local interconnect over the second local interconnect, electrically coupling the second local interconnect and the gates of the first PMOS and NMOS, the fourth local interconnect formed at least partially within and substantially co-planer with a top surface of the second dielectric layer.
Dependencies are inferred from the claim text.