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US 2009/0014780 A1Published application
Discrete trap non-volatile multi-functional memory device
AssigneeMicron Technology, Inc.
InventorArup Bhattacharyya
Life of this patent
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Abstract
A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.
Claims19
A memory cell comprising:
- a substrate having a plurality of implanted regions;
- a multiple layer tunnel dielectric formed over the substrate, the tunnel dielectric comprising a first layer of HfO2 formed over the substrate, an oxide layer formed over the first layer, and a layer of LaAlO3 formed over the oxide layer;
- a charge trapping layer formed over the tunnel dielectric;
- and
- a charge blocking layer formed over the charge trapping layer.
2 more elements
A memory cell comprising:
- a substrate having a plurality of implanted regions;
- a multiple layer tunnel dielectric formed over the substrate, the tunnel dielectric comprising a first layer of HfO2 formed over the substrate and a second layer of LaAlO3 formed over the first layer;
- a charge trapping layer formed over the tunnel dielectric;
- and
- a charge blocking layer formed over the charge trapping layer.
2 more elements
A memory cell comprising:
- a substrate having a plurality of implanted regions;
- a multiple layer tunnel dielectric formed over the substrate, the tunnel dielectric comprising a first layer of HfO2 formed over the substrate, a second layer of LaAlO3 formed over the first layer, and a third layer of HfO2 formed over the second layer;
- a charge trapping layer formed over the tunnel dielectric;
- and
- a charge blocking layer formed over the charge trapping layer.
2 more elements
A memory cell comprising:
- a substrate having a plurality of implanted regions;
- a tunnel dielectric formed over the substrate;
- a charge trapping layer formed over the tunnel dielectric;
- a multiple layer charge blocking layer formed over the charge trapping layer, the charge blocking layer including first and second laminated layers and a third layer formed between the first and second layers;
- and
- a gate formed over the charge blocking layer.
3 more elements
A method for fabricating a memory cell, the method comprising:
- forming a plurality of implanted regions in a substrate;
- forming a multiple layer tunnel dielectric over the substrate, the tunnel dielectric comprising asymmetric properties such that an electron moves from the substrate through the dielectric in response to a first energy level that is less than a second energy level that moves an electron in an opposite direction;
- forming a charge trapping layer over the tunnel dielectric;
- and
- forming a charge blocking layer over the charge trapping layer.
2 more elements
Dependencies are inferred from the claim text.