Memory device, memory and method for processing such memory
AssigneeInfineon Technologies AG
InventorsRobert Strenz, Christian Peters
Life of this patent
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Abstract
An integrated memory device, an integrated memory chip and a method for fabricating an integrated memory device is disclosed. One embodiment provides at least one integrated memory device with a drain, a source, a floating gate, a selection gate and a control gate, wherein the conductivity between the drain and the source can be controlled independently via the control gate.
Claims32
An integrated memory device comprising:
- a drain;
- a source;
- a floating gate;
- a selection gate;
- and
- a control gate configured such that the conductivity between the drain and the source can be controlled independently via the control gate.
An integrated UCP flash memory device comprising:
- a drain terminal region;
- a source terminal region;
- a floating gate layer corresponding to a first gate, namely a floating gate;
- a selection gate layer corresponding to a second gate, namely a selection gate;
- a control gate layer corresponding to a third gate, namely a control gate, defined in a self-aligning manner at least between the floating gate layer and the source terminal region.
An integrated memory device comprising:
- a drain terminal region and a source terminal region;
- a channel region arranged between the drain terminal region and the source terminal region;
- a tunneloxide layer arranged on the channel region;
- a floating gate layer arranged on a first part of the tunneloxide layer;
- a first insulating layer arranged on the floating gate layer;
- a selection gate layer arranged on the first insulating layer;
- a second insulating layer arranged on the selection gate layer;
- a control gate layer corresponding to a control gate and arranged at least on a second part of the tunneloxide layer;
- and
- a sidewall isolation arranged to isolate the control gate layer from the floating gate layer and the selection gate layer.
Method for fabricating an integrated memory device the method comprising:
- forming at least a drain terminal region, a source terminal region, a floating gate layer, a selection gate layer and a control gate layer;
- and
- forming the control gate layer at least partly on a tunneloxide layer which is arranged between the drain terminal region and the source terminal region.
A method for fabricating an integrated memory device the method comprising:
- forming a drain terminal region and a source terminal region;
- forming a tunneloxide layer between the drain terminal region and the source terminal region;
- forming a floating gate layer on a first part of the tunneloxide layer;
- forming a first insulating layer on the floating gate layer;
- forming a selection gate layer on the first insulating layer;
- forming a second insulating layer on the selection gate layer;
- forming a sidewall isolation adjacent to at least the edges of the floating gate layer, the first insulating layer, the selection gate layer and the second insulating layer facing towards the source terminal region;
- and
- forming a control gate layer at least on a second part of the tunneloxide layer.
Dependencies are inferred from the claim text.