US 2009/0014772 A1Published application

Eeprom memory cell with first-dopant-type control gate transistor, and second-dopant type program/erase and access transistors formed in common well

AssigneeMaxim Integrated Products, Inc.

InventorsNirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu

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Abstract

A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.

Claims24

Dependent claims

A memory device, comprising:

a substrate doped with a first-type dopant;
a plurality of electrically-conductive bit lines extending along a bit line direction;
a plurality of electrically-conductive word lines extending along a word line direction;
a plurality of electrically-conductive control gate lines extending along said word line direction;
and
a plurality of memory cells arranged respectively along said bit lines and said word lines, wherein each memory cell comprises:
a program/erase transistor including a first gate, and first and second terminals formed within a well doped with a second-type dopant, wherein the well is formed within said substrate, and further wherein said first terminal of the program/erase transistor is electrically connected to a corresponding bit line;
an access transistor including a second gate, and third and fourth terminals formed within said well, wherein said third terminal is electrically connected to said second terminal of said program/erase transistor, and further wherein said second gate is electrically connected to a corresponding word line;
and
a control gate transistor formed in an isolated first-type dopant region which, in turn, is formed within said well, wherein said control gate transistor comprises a third gate, and fifth and sixth terminals formed within said isolated first-type dopant region, wherein said fifth and sixth terminals are electrically connected to a corresponding control gate line, and further wherein said third gate is electrically connected to said first gate of said program/erase transistor to form a floating gate.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/233,294Filed 18 Sep 2008
Priority: 12 Mar 2007
Published: 15 Jan 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 16/0441
Comprising cells containing floating gate transistors: comprising cells containing multiple floating gate devices, e.g. separate read-and-write…
G11C 16/3427
Disturbance prevention or evaluation; Refreshing of disturbed memory data: circuits or methods to prevent or reduce disturbance of the state of a…
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 41/60
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: the control gate being a doped region, e.g. single-poly…

Family

Application11/685,111Continuation · filed 12 Mar 2007
Application12/233,294Continuation
US 2008/0225601 A1Published application
US 7,436,710 B2Related patent
US 7,835,184 B2Related patent
US 2009/0014772 A1This patent

From the US filing history. Foreign family members aren’t listed.