Non-volatile memory device and fabrication method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorMyoung-Soo KIM
Life of this patent
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Abstract
In one embodiment, a non-volatile memory device includes an isolation film defining an active region in a semiconductor substrate; a tunnel insulating film located on the active region; a control gate located on the isolation film; an inter-gate dielectric film parallel to the control gate and located between the control gate and the isolation film; an electrode overlapped by the control gate and the inter-gate dielectric film, wherein the electrode extends over the tunnel insulating film on the active region to form a floating gate; and a source region and a drain region formed in the active region on both sides of the floating gate.
Claims13
A non-volatile memory device comprising:
- an isolation film defining an active region in a semiconductor substrate;
- a tunnel insulating film located on the active region;
- a control gate located on the isolation film;
- an inter-gate dielectric film parallel to the control gate and located between the control gate and the isolation film;
- an electrode overlapped by the control gate and the inter-gate dielectric film, wherein the electrode extends over the tunnel insulating film on the active region to form a floating gate;
- and
- a source region and a drain region formed in the active region on both sides of the floating gate.
A non-volatile memory device comprising:
- a semiconductor substrate;
- an access transistor comprising:
- a tunnel insulating film on the substrate;
- a floating gate formed on the tunnel insulating film;
- an inter-gate dielectric film on the floating gate;
- and
- a control gate on the inter-gate dielectric film, wherein the control gate controls the floating gate;
- and
- a capacitor comprising:
- a capacitor lower electrode on the substrate, wherein the capacitor lower electrode and the floating gate comprise the same film;
- a capacitor dielectric layer on the capacitor lower electrode, wherein the capacitor dielectric layer and the inter-gate dielectric film comprise the same film;
- and
- a capacitor upper electrode on the capacitor dielectric layer, wherein the capacitor upper electrode and the control gate comprise the same film,
- wherein the capacitor lower electrode and the capacitor upper electrode constitute a spread capacitor structure.
A non-volatile memory device comprising:
- an access transistor comprising:
- a tunnel insulating film formed on a semiconductor substrate;
- a floating gate formed on the tunnel insulating film;
- and
- a source region and a first drain region formed on both sides of the floating gate;
- a select transistor comprising:
- a first gate insulating film formed on the semiconductor substrate;
- a select gate formed on the first gate insulating film, wherein the select gate is structurally adjacent to the access transistor;
- and
- a second drain region formed on a side of the select gate, wherein the source region is formed on another side of the select gate such that the source region is shared by the access transistor and the select transistor;
- and
- a capacitor comprising:
- a protective insulating film formed on the semiconductor substrate;
- a capacitor lower electrode formed on the protective insulating film, wherein the capacitor lower electrode comprises the same film as the floating gate of the access transistor;
- a capacitor dielectric film formed on the capacitor lower electrode;
- and
- a capacitor upper electrode formed on the capacitor dielectric film.
Dependencies are inferred from the claim text.