Semiconductor device with large blocking voltage
AssigneeRenesas Technology Corp.
InventorsHaruka Shimizu, Hidekatsu Onose
Life of this patent
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Abstract
A junction FET having a large gate noise margin is provided. The junction FET comprises an n− layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n− layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.
Claims18
A semiconductor device comprising:
- a semiconductor element made of silicon carbide as a base material having a plurality of diodes incorporated over a chip of the semiconductor element,
- wherein a first diode of the plurality of diodes has an anode connected to a gate of the semiconductor element and a cathode connected to a gate pad of the chip, and
- wherein a second diode of the plurality of diodes has a cathode connected to the gate of the semiconductor element and an anode connected to the gate pad of the chip.
A semiconductor device, comprising:
- a semiconductor element made of silicon carbide as a base material;
- and
- a gate drive circuit for the semiconductor element,
- wherein the gate drive circuit comprises a plurality of diodes connected in anti-parallel immediately before an output terminal in the gate drive circuit, and
- wherein a built-in potential of a second diode connected in a forward direction with respect to a gate of the semiconductor element is higher than a built-in potential of a first diode connected in a reverse direction with respect to the gate of the semiconductor element.
A semiconductor device, comprising:
- a silicon carbide substrate including a first electrode and a second electrode over a first surface and a third electrode over a second surface opposite to the first surface;
- a gate-controlled type transistor provided over a main surface of the silicon carbide substrate;
- and
- a diode provided over the main surface of the silicon carbide substrate,
- wherein the first electrode is electrically connected to a gate of the transistor,
- wherein the second electrode and the third electrode are electrically connected to a drift region of the transistor, and
- wherein the diode is electrically connected between the first electrode and the gate.
A semiconductor device, comprising:
- a silicon carbide substrate including a first electrode and a second electrode over a first surface and a third electrode over a second surface opposite to the first surface;
- a junction FET provided over a main surface of the silicon carbide substrate;
- and
- a diode provided over the main surface of the silicon carbide substrate,
- wherein the main surface of the silicon carbide substrate of the first conductivity type is provided with a drift region of a first conductivity type of the junction FET,
- wherein the main surface of the silicon carbide substrate is provided with a gate region of a second conductivity type opposite to the first conductivity type contacting with the drift region,
- wherein the first electrode is electrically connected to the gate region,
- wherein the second electrode and the third electrode are electrically connected to the drift region of the junction FET, and
- wherein the diode is electrically connected between the first electrode and the gate region.
Dependencies are inferred from the claim text.