Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions

A memory, comprising:

• a cell array including a plurality of cells, each cell including a bipolar junction selection transistor, each selection transistor having a first, a second and a control region, said cell array including:
• a body of semiconductor material having a surface and including a common region of a first conductivity type, the common region forming each second region of said selection transistors;
• and
• a plurality of shared control regions, of a second conductivity type, overlying said common region;
• a plurality of insulating regions formed below said surface and laterally delimiting the shared control regions;
• wherein said first regions are formed in projecting regions extending above the surface of said body, the projecting regions being laterally delimited by a grid-like layer of insulating material extending above said surface, said first regions having the first conductivity type.

A system, comprising:

• a processor;
• and
• a cell array coupled to the processor, the cell array including a plurality of cells, each cell including a bipolar junction selection transistor, each selection transistor having a first, a second and a control region, said cell array including:
• a body of semiconductor material having a surface and including a common region of a first conductivity type, the common region forming each second region of said selection transistors;
• and
• a plurality of shared control regions, of a second conductivity type, overlying said common region;
• a plurality of insulating regions formed below said surface and laterally delimiting the shared control regions;
• wherein said first regions are formed in projecting regions extending above the surface of said body, the projecting regions being laterally delimited by a grid-like layer of insulating material extending above said surface, said first regions having the first conductivity type.