# US 2008/0313581 A1 · Independent migration of hierarchical designs with methods of finding and fixing opens during migration

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- Number: US 2008/0313581 A1
- Document ID: US20080313581A1
- Status: Published application
- Kind: A1
- Application number: 11/762,832
- Filed: 2007-06-14
- Published: 2008-12-18
- Earliest claimed: 2007-06-14
- Assignees: International Business Machines Corporation
- Inventors: Veit Gernhoefer; Matthew T. Guzowski; Jason D. Hibbeler; Kevin W. McCullen; Rani Narayan; Stephen L. Runyon; Leon J. Sigal; Robert F. Walker; Pieter J. Woeltgens; Xiaoyun K. Wu; Xin Yuan
- Web page: https://patentgrep.com/patent/US20080313581A1

## CPC

- G06F 30/30: Circuit design
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.

## Claims

### Claim 1

A method for migrating a macro in an integrated circuit, the method comprising:
determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy;
migrating the base cell independently with respect to the macro based on the interface strategy;
initially scaling the macro;
swapping the migrated base cell into the macro; and
legalizing content of the initially scaled macro.

### Claim 2 (depends on 1)

The method of claim 1, wherein in the migrating, the interface element is scaled uniformly with respect to a cell boundary of the base cell.

### Claim 3 (depends on 2)

The method of claim 2, wherein the interface element includes at least one of a pin required to be connected to a macro wiring of the macro and a blockage structure required to accommodate a macro wiring.

### Claim 4 (depends on 1)

The method of claim 1, wherein in the swapping, the content of the initially scaled macro remains unchanged.

### Claim 5 (depends on 1)

The method of claim 1, wherein in the legalizing, the migrated base cell remains unchanged.

### Claim 6 (depends on 1)

The method of claim 1, for a cell level shape of the base cell that abuts a macro level shape of the macro, further comprising detecting whether an open exists between a migrated version of the cell level shape and an initially scaled version of the macro level shape.

### Claim 7 (depends on 6)

The method of claim 6, wherein the detecting includes:
creating a union shape based on the cell level shape and the macro level shape;
scaling the union shape uniformly with respect to the initial scaling of the macro; and
comparing the scaled union shape with the migrated version of the cell level shape and the initially scaled version of the macro level shape to determine an open.

### Claim 8 (depends on 7)

The method of claim 7, wherein the comparing includes superimposing the scaled union shape onto the migrated version of the cell level shape and the initially scaled version of the macro level shape.

### Claim 9 (depends on 7)

The method of claim 7, further comprising fixing a detected open before the legalizing.

### Claim 10 (depends on 9)

The method of claim 9, wherein the fixing is implemented by at least one of: an optimization of the scaled version of the macro level shape and a patching on the detected open.

### Claim 11

A method of determining a relative position between an updated version of a macro level shape and an updated version of a cell level shape, the macro level shape and the cell level shape abutting one another in an original integrated circuit layout, the method comprising:
creating a union shape based on the cell level shape and the macro level shape in the original integrated circuit layout;
updating the union shape in a same manner as the macro level shape is updated; and
comparing the updated union shape with the updated version of the cell level shape and the updated version of the macro level shape to determine the relative position.

### Claim 12 (depends on 11)

The method of claim 11, wherein the comparing includes superimposing the updated union shape onto the updated version of the cell level shape and the updated version of the macro level shape.