# US 2008/0307293 A1 · Computational efficient convolutional coding with rate matching

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2008/0307293 A1
- Document ID: US20080307293A1
- Status: Published application
- Kind: A1
- Application number: 12/133,498
- Filed: 2008-06-05
- Published: 2008-12-11
- Earliest claimed: 2007-06-08
- Assignees: Telefonaktiebolaget L M Ericsson (publ)
- Inventors: Jung-Fu Thomas Cheng
- Web page: https://patentgrep.com/patent/US20080307293A1

## CPC

- H03M 13/2732: {Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver}
- H03M 13/23: using convolutional codes, e.g. unit memory codes
- H03M 13/235: {Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding}
- H03M 13/27: using interleaving techniques
- H03M 13/2792: {Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing}
- H03M 13/2957: {Turbo codes and decoding}
- H03M 13/6356: {by repetition or insertion of dummy data, i.e. rate reduction}
- H03M 13/6362: {by puncturing}
- H04L 1/0059: {Convolutional codes}
- H04L 1/0069: {Puncturing patterns}
- H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

## Claims

### Claim 1

An error coding circuit comprising:
a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits;
an interleaver circuit for interleaving parity bits within each group of parity bits; and
a rate-matching circuit for outputting a selected number of said interleaved parity bits ordered by group to obtain a desired code rate.

### Claim 2 (depends on 1)

The error coding circuit of claim 1 wherein said rate matching circuit includes a circular buffer storing said interleaved parity bits ordered by group.

### Claim 3 (depends on 1)

The error coding circuit of claim 1 wherein said rate matching circuit comprises a group multiplexing circuit.

### Claim 4 (depends on 1)

The error coding circuit of claim 1 wherein said interleaver circuit is configured to apply identical interleaving for each group of parity bits.

### Claim 5 (depends on 1)

The error coding circuit of claim 1 wherein said interleaver circuit is configured to apply different interleaving for each group of parity bits

### Claim 6 (depends on 1)

The error coding circuit of claim 1 wherein said rate matching circuit outputs odd parity bits within each group prior to even parity bits.

### Claim 7 (depends on 6)

The error coding circuit of claim 6 wherein said interleaver circuit is configured to order parity bits such that the odd parity bits precede the even parity bits within each group of parity bits.

### Claim 8 (depends on 7)

The error coding circuit of claim 7 wherein said interleaver circuit implements a reverse bit reverse order interleaver for column permutation.

### Claim 9 (depends on 7)

The error coding circuit of claim 7 wherein said interleaver circuit implements a cyclically-shifted bit reverse order interleaver for column permutation.

### Claim 10 (depends on 7)

The error coding circuit of claim 7 wherein said interleaver circuit implements a modulo-offset bit reverse order interleaver for column permutation.

### Claim 11

A method for error coding an input bit stream, said method comprising:
coding said input bit stream in a non-systematic convolutional encoder to produce two or more groups of parity bits;
interleaving parity bits within each group of parity bits; and
outputting a selected number of said interleaved parity bits ordered by group to obtain a desired code rate.

### Claim 12 (depends on 11)

The method of claim 11 further comprising storing said interleaved parity bits ordered by group in a circular buffer, and wherein said interleaved parity bits are output from said circular buffer.

### Claim 13 (depends on 11)

The method of claim 11 further comprising group multiplexing said parity bits in a group multiplexing circuit while said bits are being output.

### Claim 14 (depends on 11)

The method of claim 11 wherein identical interleaving is applied to each group of parity bits.

### Claim 15 (depends on 11)

The method of claim 11 wherein different interleaving is applied to each group of parity bits

### Claim 16 (depends on 11)

The method of claim 11 wherein outputting a selected number of said interleaved parity bits ordered by group to obtain a desired code rate further comprises outputting odd parity bits within each group before outputting even parity bits.

### Claim 17 (depends on 16)

The method of claim 16 wherein said interleaving orders parity bits such that the odd parity bits precede the even parity bits within each group of parity bits.

### Claim 18 (depends on 17)

The method of claim 17 wherein said interleaving comprises a reversed bit reverse order interleaving for column permutation.

### Claim 19 (depends on 17)

The method of claim 17 wherein said interleaving comprises a cyclically-shifted bit reverse order interleaving for column permutation.

### Claim 20 (depends on 17)

The method of claim 17 wherein said interleaving comprises a modulo-offset bit reverse order interleaving for column permutation.