Redundancy circuit

A redundancy circuit comprising:

• a first fuse set circuit that includes a plurality of first fuse sets which is configured to receive an address signal and an initializing signal activated when power is up and to output a plurality of first redundancy signals;
• a second fuse set circuit that includes a plurality of second fuse sets which is configured to receive the initializing signal, a specific address signal, a test mode signal that is activated when a defective cell is existent, and the address signal and to output a plurality of second redundancy signals;
• a first memory cell array that is controlled by the first redundancy signals;
• and
• a second memory cell array that is controlled by the second redundancy signals,
• wherein the first fuse set is configured to output the first redundancy signal for driving a redundancy word line of the first memory cell array in response to a defective memory cell occurring in a wafer state, and
• the second fuse set is configured to output the second redundancy signal for driving a redundancy word line of the second memory cell array in response to a defective memory cell occurring in the wafer state and a package state.