A/D converter
AssigneesFujitsu Limited, Fujitsu Electronics Inc.
InventorMasahito Ishizawa
Life of this patent
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Abstract
An A/D converter capable of generating an interrupt for requesting a control circuit to read the results of A/D conversion, in desired timing. Analog signals input from channels selected by a channel-selecting section are input to an A/D conversion section, and are sequentially A/D-converted. The results of A/D conversion are sequentially stored in different stages of a FIFO. A stage number-counting section counts the number of the stages of the FIFO where the results of A/D conversion are stored. An interrupt signal-delivering section outputs an interrupt signal for requesting a CPU to read the results of A/D conversion when the number of stages counted by the stage number-counting section is equal to an interrupt-generating stage number set by an interrupt-generating stage number-setting section.
Claims7
An A/D converter for A/D-converting analog signals input from a plurality of channels, comprising:
- a channel-selecting section selecting channels from said channels, for A/D conversion of the analog signals;
- an A/D conversion section sequentially A/D-converting the analog signals from the selected channels on a channel-by-channel basis;
- a FIFO comprising a plurality stages of storage areas, and sequentially storing results of A/D conversion on a channel-by-channel basis in different ones of the stages;
- a stage number-counting section counting a number of stages of said FIFO where the results of A/D conversion are stored;
- an interrupt-generating stage number-setting section setting a interrupt-generating stage number;
- and
- an interrupt signal-delivering section delivering an interrupt signal for requesting a control circuit reading the results of A/D conversion to read the results of A/D conversion, when the number of stages counted by said stage number-counting section becomes equal to the interrupt-generating stage number.
Dependencies are inferred from the claim text.