# US 2008/0303084 A1 · Vertical Tunneling Transistor

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- Number: US 2008/0303084 A1
- Document ID: US20080303084A1
- Status: Published application
- Kind: A1
- Application number: 12/191,175
- Filed: 2008-08-13
- Published: 2008-12-11
- Earliest claimed: 2003-08-27
- Assignees: Micron Technology, Inc.
- Inventors: Gurtej S. Sandhu
- Web page: https://patentgrep.com/patent/US20080303084A1

## CPC

- H10D 30/688: {programmed by two single electrons}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- Y10S 977/943: Information storage or retrieval using nanostructure
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may be disposed so that an axis through the channel, the quantum dot and the gate is substantially perpendicular to the substrate.

## Claims

### Claim 1

An electronic device, comprising:
a memory device that receives information stored on the storage device, the memory device comprising:
a substrate;
a plurality of access transistors, each of the plurality of access transistors comprising:
a channel formed on the substrate;
a self-aligned island of conductive material formed such that the channel is between the island of conductive material and the substrate;
a gate formed such that the island of conductive material is between the gate and the channel; and
wherein an axis through the channel, the island of conductive material, and the gate is substantially perpendicular to an upper surface of the substrate; and
a memory array including a plurality of memory cells formed on the substrate, each of the plurality of memory cells comprising of a memory element coupled to one of the plurality of access transistors.

### Claim 2 (depends on 1)

The electronic device set forth in claim 1, further comprising a processor adapted to execute instructions.

### Claim 3 (depends on 2)

The electronic device set forth in claim 2, further comprising a storage device adapted to store data, the data at least partially comprising instructions to be executed by the processor.

### Claim 4 (depends on 3)

The electronic device set forth in claim 3, further comprising a user input device adapted to receive data for use by the processor from a user.

### Claim 5 (depends on 4)

The electronic device set forth in claim 4, further comprising a display device adapted to produce an image for viewing by a user based on instructions executed by the processor.

### Claim 6

A memory device, comprising:
a memory element disposed on a substrate; and
an access device coupled to the memory element, the access device comprising:
a channel formed on the substrate;
an island of conductive material formed such that an axis through the channel and the island of conductive material is substantially perpendicular to the substrate; and
a gate formed such that an axis through the channel, the island of conductive material and the gate is substantially perpendicular to the substrate.

### Claim 7 (depends on 6)

The memory device set forth in claim 6, comprising a source formed adjacent to the channel.

### Claim 8 (depends on 6)

The memory device set forth in claim 6, comprising a drain formed adjacent to the channel.

### Claim 9 (depends on 6)

The memory device set forth in claim 6, comprising a tunneling barrier formed between the channel and the island of conductive material.

### Claim 10 (depends on 6)

The memory device set forth in claim 6, comprising an insulative layer formed between the island of conductive material and the gate.

### Claim 11

An integrated circuit device, comprising:
a substrate; and
a memory array that includes a plurality of memory cells disposed on the substrate, each of the plurality of memory cells comprising a memory element and an access transistor, the access transistor comprising:
a channel disposed on the substrate;
a self-aligned island of conductive material disposed so that the channel is between the island of conductive material and the substrate;
a gate disposed so that the island of conductive material is between the gate and the channel; and
wherein an axis through the channel, the island of conductive material, and the gate is substantially perpendicular to an upper surface of the substrate.

### Claim 12 (depends on 11)

The integrated circuit device set forth in claim 11, wherein the memory element is coupled to the access transistor.

### Claim 13

A device comprising:
a memory element disposed on a substrate, and
an access device coupled to the memory element, the access device comprising:
a channel disposed on the substrate;
an island of conductive material disposed so that the channel is between the island of conductive material and the substrate;
a gate disposed so that the island of conductive material is between the gate and the channel; and
wherein an axis through the channel, the island of conductive material, and the gate is substantially perpendicular to an upper surface of the substrate.

### Claim 14

A vertical tunneling transistor, the vertical tunneling transistor produced by the process of:
disposing a channel on a substrate;
disposing a dielectric layer on the substrate;
providing an aperture with a sidewall in the dielectric layer;
disposing a spacer adjacent the sidewall in the aperture that reduces a dimension of the aperture that is substantially parallel to the substrate to a sub-photolithographic size;
disposing an island of conductive material within the aperture so that an axis through the channel and the island of conductive material is substantially perpendicular to the substrate; and
providing a gate so that an axis through the channel, the island of conductive material and the gate is substantially perpendicular to the substrate.

### Claim 15 (depends on 14)

The vertical tunneling transistor set forth in claim 14, wherein the process comprises employing atomic layer deposition to provide the channel.

### Claim 16 (depends on 14)

The vertical tunneling transistor set forth in claim 14, wherein the process comprises employing atomic layer deposition to provide the island of conductive material.

### Claim 17 (depends on 14)

The vertical tunneling transistor set forth in claim 14, wherein the process comprises employing atomic layer deposition to provide the gate.

### Claim 18 (depends on 14)

The vertical tunneling transistor set forth in claim 14, wherein the process comprises providing a tunneling barrier.

### Claim 19 (depends on 18)

The vertical tunneling transistor set forth in claim 18, wherein the process comprises employing atomic layer deposition to provide a tunneling barrier.

### Claim 20 (depends on 14)

The vertical tunneling transistor set forth in claim 14, wherein the process comprises providing an insulative layer.

### Claim 21 (depends on 20)

The vertical tunneling transistor set forth in claim 20, wherein the process comprises employing atomic layer deposition to provide an insulative layer.

### Claim 22

A memory device, comprising:
a memory element formed on a substrate; and
an access device coupled to the memory element, the access device comprising:
a channel formed on the substrate;
a self-aligned island of conductive material formed such that the channel is between the island of conductive material and the substrate;
a gate formed such that the island of conductive material is between the gate and the channel; and
wherein an axis through the channel, the island of conductive material, and the gate is substantially perpendicular to an upper surface of the substrate.