Method and System for Testing Bit Failures in Array Elements of an Electronic Circuit
AssigneeInternational Business Machines Corporation
InventorsJoachim Kneisel, Otto Torreiter
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Abstract
The invention relates to a method and system for testing bit failures in array elements of an electronic circuit. Said method comprising the steps of changing an original hardware representation (DD) of the array such that errors can be injected in a memory by manipulation of associated read and/or write logic of the memory via input signals, building an emulator model (SME) from said changed hardware representation for emulating the array, and injecting errors into the changed hardware representation for determining the array to get stick capabilities.
Claims20
A method for testing bit failures in array elements of an electronic circuit, said method comprising the steps of:
- Modifying a representation (DD) of said electronic circuit such that errors can be injected in the memory of array elements via input signals of read and/or write logic of said array elements;
- Building an emulator model (SME) from the modified representation;
- and
- Injecting errors into said array elements during an emulation of said emulator model.
A computer program loadable into the internal memory of a digital computer system comprising software code portions for performing a method comprising:
- Modifying a representation (DD) of said electronic circuit such that errors can be injected in the memory of array elements via input signals of read and/or write logic of said array elements;
- Building an emulator model (SME) from the modified representation;
- and
- Injecting errors into said array elements during an emulation of said emulator model.
An emulation system, also comprising a computer program loaded in the internal memory of a computer, adapted for performing in the method of:
- Modifying a representation (DD) of said electronic circuit such that errors can be injected in the memory of array elements via input signals of read and/or write logic of said array elements;
- Building an emulator model (SME) from the modified representation;
- and
- Injecting errors into said array elements during an emulation of said emulator model;
- said emulation system connected to tester hardware.
Dependencies are inferred from the claim text.