Method For Automatic Clock Gating To Save Power
AssigneeMagma Design Automation, Inc.
InventorsYunjian (William) Jiang, Arvind Srinivasan, Joy Banerjee, Yinghua Li, Partha Das, Samit Chaudhuri
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Abstract
A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.
Claims28
A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the method comprising:
- identifying a plurality of blocks in the synthesized netlist as idle candidate blocks;
- determining a clock gating structure optimized for power savings based on the idle candidate blocks;
- identifying inflexible clock gates to be inserted in the netlist;
- performing global placement of each element of the netlist on a chip;
- clustering sub-blocks on the chip into a plurality of placement-driven clusters;
- determining, for each of the plurality of placement-driven clusters, whether to insert a flexible clock gate on the chip based on an evaluation of each of the plurality of placement-driven clusters;
- performing detailed placement of each element of the netlist on the chip;
- and
- tuning the inserted flexible clock gate based on an analysis of each of the plurality of placement-driven clusters that includes the inserted flexible clock gate.
A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the method comprising:
- identifying a block in the synthesized netlist as an idle candidate block;
- determining a clock gating structure optimized for power savings based on the idle candidate block;
- and
- identifying an inflexible clock gate to be inserted in the netlist.
A computer program product stored on a computer-readable medium for deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the computer program product comprising:
- code for identifying a block in the synthesized netlist as an idle candidate block;
- code for determining a clock gating structure optimized for power savings based on the idle candidate block;
- and
- code for identifying an inflexible clock gate to be inserted in the netlist.
A system for deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the system comprising:
- a processor;
- and
- a memory coupled to the processor, the memory configured to store a plurality of code modules which when executed by the processor cause the processor to:
- identify a block in the synthesized netlist as an idle candidate block;
- determine a clock gating structure optimized for power savings based on the idle candidate block;
- and
- identify an inflexible clock gate to be inserted in the netlist.
A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the method comprising:
- identifying a block in the synthesized netlist as an idle candidate block;
- clustering sub-blocks on the chip into a cluster;
- determining, for the cluster, a clock gating structure optimized for power savings based on the idle candidate block;
- and
- inserting one or more inflexible clock gates in the netlist according to the clock gate structure.
A computer program product stored on a computer-readable medium for deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the computer program product comprising:
- code for identifying a block in the synthesized netlist as an idle candidate block;
- code for clustering sub-blocks on the chip into a cluster;
- code for determining, for the cluster, a clock gating structure optimized for power savings based on the idle candidate block;
- and
- code for inserting one or more inflexible clock gates in the netlist according to the clock gate structure.
A system for deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the system comprising:
- a processor;
- and
- a memory coupled to the processor, the memory configured to store a plurality of code modules which when executed by the processor cause the processor to:
- identify a block in the synthesized netlist as an idle candidate block;
- cluster sub-blocks on the chip into a cluster;
- determine, for the cluster, a clock gating structure optimized for power savings based on the idle candidate block;
- and
- insert one or more inflexible clock gates in the netlist according to the clock gate structure.
Dependencies are inferred from the claim text.