US 2008/0301511 A1 · INTEGRATED CIRCUIT WITH CONTINUOUS TESTING OF REPETITIVE FUNCTIONAL BLOCKS

Abstract

A method of continuous testing of repetitive functional blocks provided on an integrated circuit (IC) which includes selecting one of the repetitive functional blocks at a time for testing, substituting a test repetitive functional block for a selected repetitive functional block, and testing the selected repetitive functional block during normal functional mode of the IC. An IC which includes repetitive functional blocks for performing corresponding functional block operations during normal functional mode of the IC, and a test system which performs continuous testing of each repetitive functional block while the functional block operations are performed during normal functional mode of the IC. One block may be tested during normal operation for each IC reset event without transferring or copying state information. Multiple blocks may be tested one at a time during normal operation by transferring state information between a selected block and a test block.

Claims20

Dependent claims

A method of continuous testing of a plurality of repetitive functional blocks provided on an integrated circuit, comprising:

selecting one of the plurality of repetitive functional blocks at a time for testing;
substituting a test repetitive functional block for a selected repetitive functional block, wherein the test repetitive functional block performs operations of the selected repetitive functional block;
and
testing the selected repetitive functional block during normal functional mode of the integrated circuit.

1 more element

An integrated circuit, comprising:

a plurality of repetitive functional blocks for performing a plurality of functional block operations during normal functional mode of said integrated circuit;
and
a test system, coupled to said plurality of repetitive functional blocks, which performs continuous testing of each of said plurality of repetitive functional blocks while performing each of said plurality of functional block operations during said normal functional mode.

A test system provided on an integrated circuit, comprising:

a plurality of repetitive functional blocks representing a plurality of physical identifications;
mapping logic, coupled to said plurality of repetitive functional blocks, comprising a plurality of logical identifications mapped to said plurality of physical identifications, each of said plurality of logical identifications comprising a corresponding mapping of input and output signals of said plurality of repetitive functional blocks;
and
a test system, coupled to said plurality of repetitive functional blocks and said mapping logic, which tests a first physical identification of said plurality of repetitive functional blocks while a first logical identification is mapped from said first physical identification to a second physical identification of said plurality of repetitive functional blocks during said normal functional mode of the integrated circuit.

1 more element

Dependencies are inferred from the claim text.

Integrated circuit with continuous testing of repetitive functional blocks

Life of this patent

Integrated circuit with continuous testing of repetitive functional blocks

Life of this patent

Abstract

Claims20